Vendor: Siemens Tessent Embedded Analytics Category: CPU

Tessent RISC-V trace and debug

The Tessent Enhanced Trace Encoder is the market- trace solution for RISC-V.

RISC-V View all specifications

Overview

The Tessent Enhanced Trace Encoder is the market-leading trace solution for RISC-V. It is a fully-featured solution that provides a mechanism to monitor the program execution of a CPU in real time. It encodes program execution (instruction trace) and optionally, the data from load and store instructions (data trace), outputting trace in a highly compressed format.

The Tessent Enhanced Trace Encoder is designed to meet the official RISC-V Efficient Trace (E-trace) specification produced by the Debug and Trace Working Group. This group was led by representatives from Siemens who donated the trace algorithm to the RISC-V International community.

In addition to providing all the mandatory and optional features defined in the E-trace specification, the Tessent Enhanced Trace Encoder is cycle accurate, which means the developer gets insights into each and every instruction.

All Tessent Embedded Analytics monitors (IPs), can be accessed via a dedicated, secure communication infrastructure. Non-intrusive debug and monitoring using an off-chip host or debugger is facilitated through USB 2, USB 3, JTAG, or Aurora interfaces. Embedded software can drive the system via an AXI interface to create a self-contained on-chip monitoring system.

Key features

  • Instruction trace
  • Efficient packet format
  • Fast profiling
  • Multiple retirement
  • Data trace
  • Filters and comparators
  • Timestamps
  • Implicit return mode
  • Branch prediction
  • Jump target cache mode
  • Implicit exception mode
  • Sequentially inferable jump mode
  • Cycle accurate trace

Block Diagram

Tessent RISC-V trace and debug block diagram

Benefits

  • The most capable RISC-V trace solution on the market
  • Part of the Tessent Embedded Analytics whole system solution

What’s Included?

  • Parameterized soft core (Verilog RTL)
  • Verification trace decoder
  • Available UVM verification IP

Specifications

Identity

Part Number
Tessent RISC-V trace and debug
Vendor
Siemens Tessent Embedded Analytics
Type
Silicon IP

Compute

CPU Architecture
RISC-V

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Learn more about CPU IP core

Debugging complex RISC-V processors

To debug and profile a RISC-V processor that comprises tens or hundreds of cores and processes billions of instructions each second can be challenging. Is the software running as expected? Does the verification team see the same behavior as the firmware engineers or application developers?

Frequently asked questions about CPU IP cores

What is Tessent RISC-V trace and debug?

Tessent RISC-V trace and debug is a CPU IP core from Siemens Tessent Embedded Analytics listed on Semi IP Hub.

How should engineers evaluate this CPU?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this CPU IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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