SSI (Synchronous Serial Interface) Verification IP

The SmartDV Verification IP (VIP) for SSI (Synchronous Serial Interface) is a full-duplex synchronous serial interface and can connect to a variety of external analog-to-digital (A/D) converters, audio and telecom codecs, and other devices that use serial protocols for transferring data. The SmartDV Verification IP for SSI is fully compliant with TM4C123GH6PM SSI module specification and provides the following features:

SSI (Synchronous Serial Interface) Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

SSI (Synchronous Serial Interface) Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

• Implemented in native OpenVera, Verilog, SystemC and SystemVerilog.
• Supported RVM, AVM, VMM, OVM, UVM and non-standard verify Env.
• Fully compatible with TM4C123GH6PM SSI modules SSI Specification.
• Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments synchronous serial interfaces.
• Master or Slave operation.
• Programmable clock bit rate and prescaler.
• Separate transmit and receive FIFOs.
• Programmable data frame size from 4 to 16 bits.
• Internal loopback test mode for diagnostic/debug testing.
• Standard FIFO-based interrupts and End-of-Transmission interrupt.
• Efficient transfers using Micro Direct Memory Access Controller (μDMA).
• Separate channels for transmit and receive.
• Receive single request asserted when data is in the FIFO; burst request asserted when FIFO contains 4 entries.
• Transmit single request asserted when there is space in the FIFO; burst request asserted when four or more entries are available to be written in the FIFO.
• Callbacks in Master, Slave and monitor for user processing of data.
• Notifies the test bench of significant events such as transactions, warnings, and protocol violations.
• SSI Verification IP comes with complete test suite to verify each and every feature of SSI specification.
• Status counters for various events in bus.
• Functional coverage for complete features.

• Faster test bench development and more complete verification of SSI designs.
• Easy to use command interface simplifies test bench control and configuration of Master and Slave.
• Simplifies results analysis.
• Runs in every major simulation environment

• Complete regression suite containing all the SSI testcases to certify SSI Master/Slave device.
• Examples showing how to connect various components, and usage of Master, Slave and Monitor.
• Detailed documentation of all class, task and function's used in verification env.
• Documentation also contains User's Guide and Release notes.