SPI/FRAM Verification IP

SPI/FRAM Verification IP provides an smart way to verify the serial synchronous communication protocol.The SmartDV's SPI/SPANSION_FLASH Verification IP is fully compliant with SPI Block Guide V04.01 of the FRAM's FM25L512 512Kb Memory Specification and provides the following features. It can work with Verilog HDL environment and works with all Verilog simulators that are support SystemVerilog.

SPI/FRAM Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

SPI/FRAM Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

• Follows FRAM basic specification as defined in FM25L512 512Kb
• Supports 512K bit Ferroelectric Nonvolatile RAM and Organized as 65,536 x 8 bits
• Supports Unlimited Read/Write Cycles
• Supports No delay Writes
• Supports Write Protection Scheme
• Supports Very Fast Serial Peripheral Interface up to 20 MHz Frequency
• Supports Master and Slave Mode
• Support clock polarity (CPOL) selection.
• Support clock phase (CPHA) selection.
• Supports customized single/dual/quad modes for Command, Address and Data phase
• Supports configurable dummy cycles
• Supports configurable memory density
• Supports backdoor access for memory and registers
• Built in functional coverage analysis.
• Supports Callbacks in master, slave and monitor for modifying, and sampling data/command on SPI/FRAM bus.
• SPI /FRAM Slave can be configured as standard device or can use FIFO for data passing.
• Master contains rich set of commands for both standard device and FIFO model mode.

• Faster testbench development and more complete verification of SPI/FRAM designs.
• Easy to use command interface simplifies testbench control and configuration of slave and master.
• Simplifies results analysis.
• Runs in every major simulation environment.

• Complete regression suite containing all the SPI/FRAM testcases.
• Examples showing how to connect various components, and usage of Master, Slave and Monitor.
• Detailed documentation of all class, task and function's used in verification env.
• Documentation contains User's Guide and Release notes.