Safe-By-Wire Plus Verification IP

Safe-By-Wire Plus (SBWP) Verification IP is an advanced solution in the market for the verification of Safe-By-Wire Plus (SBWP) two-wire serial communications bus. It is adherent with Safe-By-Wire Plus (SBWP) 2.0 specification. The Safe-By-Wire Plus (SBWP) Verification IP monitor acts as powerful protocol-checker, fully compliant with Safe-By-Wire Plus (SBWP) 2.0 specification.

Safe-By-Wire Plus (SBWP) 2.0 Verification IP includes an extensive test suite covering most of the possible scenarios.

Safe-By-Wire Plus Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

Safe-By-Wire Plus Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

• Adherent to Safe-By-Wire Plus 2.0 Specification.
• Supports generation of frames with error and noise injection.
• Tracking of transmit and receive counters.
• Protocol Checker fully compliant with Safe-By-Wire Plus 2.0 specification.
• Detection of bit errors by master and by slave.
• Bus-accurate timing.
• Monitor, Detects and notifies the testbench of all protocol errors.
• Supports constraints Randomization.
• Status counters for various events on bus.
• Callbacks in master, slave and monitor for various events.
• SBWP Verification IP comes with complete testsuite to test every feature of SBWP 2.0 specification.
• Functional coverage for complete SBWP 2.0 features.

• Faster testbench development and more complete verification of Safe-By-Wire Plus designs.
• Easy to use command interface simplifies testbench control and configuration of slave and master.
• Simplifies results analysis.
• Runs in every major simulation environment.

• Complete regression suite containing all the Safe-By-Wire Plus testcases.
• Examples showing how to connect various components, and usage of Master, Slave and Monitor.
• Detailed documentation of all class, task and function's used in verification env.
• Documentation contains User's Guide and Release notes.