Vendor: SmartDV Technologies Category: Protocol Bridge

OCP Assertion IP

OCP Assertion IP provides an efficient and smart way to verify the OCP designs quickly without a testbench.

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Overview

OCP Assertion IP provides an efficient and smart way to verify the OCP designs quickly without a testbench. The SmartDV's OCP Assertion IP is fully compliant with standard OCP Specification.

OCP Assertion IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

OCP Assertion IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key features

  • Specification Compliance
    • OCP 2.0/2.1/2.2 support
    • All signal level checks including X detection
    • Support transaction and transfer level checks
    • Support for all data and address widths
    • Supports all OCP protocol burst models, burst lengths and response types
    • SRMD and MRMD bursts support
    • Request interleaving support
    • Supports 2-Dimensional block burst address sequences.
    • Compliance to phase-ordering rules.
  • Assertion IP features
    • Assertion IP includes:
    • System Verilog assertions
    • System Verilog assumptions
    • System Verilog cover properties
    • Synthesizable Verilog Auxiliary code
    • Support Master mode, Slave mode, Monitor mode and Constraint mode.
    • Supports Simulation mode (stimulus from SmartDV OCP VIP) and Formal mode (stimulus from Formal tool).
    • Rich set of parameters to configure OCP Assertion IP functionality.

Block Diagram

OCP AIP block diagram

Benefits

  • Runs in every major formal and simulation environment.

What’s Included?

  • Detailed documentation of Assertion IP usage.
  • Documentation also contains User's Guide and Release notes.

Specifications

Identity

Part Number
OCP AIP
Vendor
SmartDV Technologies
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

SmartDV Technologies
HQ: India
At SmartDV Technologies™, we believe there’s a better way to approach semiconductor intellectual property (IP) for integrated circuits. We’ve been focused exclusively on IP since 2007—so whether you’re sourcing standards-based design IP for your next SoC, ASIC, or FPGA, or seeking verification solutions (VIP) to put your chip design through its paces, you’ll find SmartDV’s IP straightforward to integrate. By combining proprietary SmartCompiler™ technology with the knowledge of hundreds of expert engineers, SmartDV can customize IP to meet your unique design objectives: quickly, economically, and reliably. Don’t allow other suppliers to force one-size-fits-all cores into your chip design. Get the IP you need, tailored to your specifications, with SmartDV: IP Your Way.
Contact SmartDV Technologies

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Frequently asked questions about Protocol Bridge IP cores

What is OCP Assertion IP?

OCP Assertion IP is a Protocol Bridge IP core from SmartDV Technologies listed on Semi IP Hub.

How should engineers evaluate this Protocol Bridge?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Protocol Bridge IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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