Vendor: SmartDV Technologies Category: OBSAI

OBSAI Synthesizable Transactor

OBSAI Synthesizable Transactor provides an smart way to verify the OBSAI component of a SOC or a ASIC in Emulator or FPGA platfor…

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Overview

OBSAI Synthesizable Transactor provides an smart way to verify the OBSAI component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's OBSAI Synthesizable Transactor is fully compliant with standard OBSAI Specification and provides the following features.

Key features

  • Compliant with OBSAI Reference Point 1 Specification Version 2.1 and Reference Point 3 Specification Version 4.2
  • Supports complete OBSAI Tx/Rx functionality
  • Supports the Physical link layer of the OBSAI RP3 specification
  • Supports the Data link layer of the OBSAI RP3 specification
  • Supports test cases as per standard
    • Conformance Test Specification Version 1.01
  • Supports the different standard bit rates of the OBSAI specification
    • 768 Mbps
    • 1536 Mbps
    • 3072 Mbps
    • 6144 Mbps
  • Supports CDMA/WCDMA/802.16/LTE framing formats
  • Supports Frame Clock Burst Messages
  • Supports RTT Measurement
  • Supports Virtual Hardware Reset
  • Supports Line Rate Auto-Negotiation
  • Supports Ethernet Messaging
  • Supports Transport layer multiplexing/demultiplexing
  • Supports scrambler as in OBSAI specification
  • Supports scrambler enabling and disabling
  • Supports insertion of scrambler errors
  • Supports disparity and invalid code insertion in 8b/10b
  • Detects and reports the following errors
    • Invalid control character
    • Invalid data character
    • Invalid 10bit code
    • Scrambler errors
    • Disparity errors
    • Under and oversize frame
    • CRC errors
    • Framing errors
  • Supports glitch insertion and detection
  • Supports bus accurate timing and timing checks

Block Diagram

OBSAI Transactor block diagram

Benefits

  • Compatible with testbench writing using SmartDV's VIP
  • All UVM sequences/testcases written with VIP can be reused
  • Runs in every major emulators environment
  • Runs in custom FPGA platforms

What’s Included?

  • Synthesizable transactors
  • Examples showing how to connect and usage of Synthesizable Transactor
  • Detailed documentation of all DPI, class, task and functions used in verification env
  • Documentation also contains User's Guide and Release notes

Specifications

Identity

Part Number
OBSAI Transactor
Vendor
SmartDV Technologies
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact SmartDV Technologies

Learn more about OBSAI IP core

Forward-Looking SoC-based PHY Architecture for Macro and Small Cell LTE eNode-Bs

This paper describes an efficient, forward-looking architecture that enables handling of various form factors of LTE base stations with minimal software modification and without architecture changes. The architecture proposed allows easy migration to the next generation SoCs as well as to more powerful SoCs of the same generation. Our implementation of this architecture has now migrated two generations of SoCs for LTE Release 9 small and macro cells, and is ready for migration to a multi-sector, LTE-A macro base station.

Frequently asked questions about OBSAI IP cores

What is OBSAI Synthesizable Transactor?

OBSAI Synthesizable Transactor is a OBSAI IP core from SmartDV Technologies listed on Semi IP Hub.

How should engineers evaluate this OBSAI?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this OBSAI IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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