Vendor: SmartDV Category: Test / Debug

NAND Flash Memory Model

NAND Flash Memory Model provides an smart way to verify the NAND Flash component of a SOC or a ASIC.

Overview

NAND Flash Memory Model provides an smart way to verify the NAND Flash component of a SOC or a ASIC. The SmartDV's NAND Flash memory model is fully compliant with standard NAND Flash Specification and provides the following features. Better than Denali Memory Models.

NAND Flash Memory Model is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

NAND Flash Memory Model comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key features

  • Supports NAND Flash memory devices from all leading vendors.
  • Supports 100% of NAND FLASH protocol standard of HY27UH08AG(5/D)M.
  • Supports all the NAND FLASH commands as per the specs.
  • Provides cost effective solutions for mass storage applications.
  • Supports NAND interface of x8 width.
  • Supports multiplexed Address/Data.
  • Supports memory cell array of (2K+64) Bytes *64 Pages*16,384 Blocks.
  • Supports page size of (2K + 64 spare) Bytes for x8 device.
  • Supports Block size of (128K + 4K spare) Bytes for x8 device.
  • Supports page read/program.
  • Supports Copy back program mode for fast page copy without external buffering.
  • Supports cache program mode to improve the program throughput.
  • Supports Fast block erase time of 2ms.
  • Supports status register.
  • Supports Electronic signature.
  • Supports Chip enable don’t care.
  • Supports Hardware data protection.
  • Supports Data integrity of 100,000 program/erase cycles.
  • Notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
  • Constantly monitors NAND FLASH behavior during simulation.
  • Protocol checker fully compliant with NAND FLASH Specification HY27UH08AG(5/D).
  • Models, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
  • Built in functional coverage analysis.
  • Supports Callbacks, so that user can access the data observed by monitor.

Block Diagram

NAND Flash Memory Model block diagram

Benefits

  • Faster testbench development and more complete verification of NAND Flash designs.
  • Easy to use command interface simplifies monitor control and configuration.
  • Simplifies results analysis.
  • Runs in every major simulation environment.

What’s Included?

  • Complete regression suite containing all the NAND Flash testcases.
  • Examples showing how to connect and usage of Model.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation also contains User's Guide and Release notes.

Specifications

Identity

Part Number
NAND Flash Memory Model
Vendor
SmartDV
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

SmartDV
HQ: India

Learn more about Test / Debug IP core

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Frequently asked questions about SerDes Test / Debug IP cores

What is NAND Flash Memory Model?

NAND Flash Memory Model is a Test / Debug IP core from SmartDV listed on Semi IP Hub.

How should engineers evaluate this Test / Debug?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Test / Debug IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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