I3C 1.1.1 Verification IP
The I3C Verification IP provides an effective & efficient way to verify the components interfacing with I3C interface of an IP or…
Overview
The I3C Verification IP provides an effective & efficient way to verify the components interfacing with I3C interface of an IP or SoC.
The I3C VIP is fully compliant with Rev. 1.1.1 of I3C specifications from MIPI. This VIP is a lightweight VIP with easy plug-and-play interface so that there is no hit on the design cycle time.
Key features
- Fully compliant with Rev. 1.1.1 of the I3C-Bus Specification
- Support existent i2c bus/device. like I2C messaging, Single Data Rate messaging (SDR) and High Data Rate messaging (HDR)
- Support all modes in HDR i.e DDR, TSP, TSL and BT.
- Support Multi-Lane Data Transfer for both SDR & HDR speed modes.
- Vip’s master BFM can connect to I2C Slave Devices.
- Can work as secondary master on request.
- Support Broadcast or directed (Common Command Code) command to the slave.
- Support both dynamic and group address assignment procedures.
- Supports Device to Device(s) Tunneling and Device Early Termination capability for both write & read transfer
- Supports Pre-Handoff flow, Master to Master Handoff Procedure, Bus management and configuration procedures.
- Maximum 11 Slave can be configured.
- Support all types of roles for slave(SDR only slave and with SDR & HDR mode).
- Supports additional Multi-Drop and Hot-Join and passive Hot-Join capability
- Supports Arbitration and Clock Synchronization.
- Supports generation of transactions with UVM register model.
- Built in I3C Bus Monitor provides extensive protocol checking.
- Supports various error injection and detection.
- Provides verification scalability using functional coverage.
- Provides logging facility for bus traffic in the ASCII format and in user configurable mode.
- Supports timing checks in the Monitor.
- Callbacks for user-defined transfers.
- Supports transaction logging with detailed description of each transfer.
- Graphical analyser to show transactions for easy debugging.
Block Diagram
Benefits
- Available in native SystemVerilog (UVM/OVM/VMM) and Verilog
- Unique development methodology to ensure highest level of quality
- Availability of Conformance and Regression Test Suites
- 24x5 customer support
- Unique and customizable licensing models
- Exhaustive set of assertions and cover points with connectivity example for all the components
- Consistency of interface, installation, operation and documentation across all our VIPs
What’s Included?
- I3C Master/Slave Agent
- I3C Monitor and Score board
- Test Environment & Test Suite:
- Basic and Directed Protocol Tests
- Random Tests
- Error Scenario Tests
- Assertions & Cover Point Tests
- Integration Guide, User Manual and Release Notes
Specifications
Identity
Files
Note: some files may require an NDA depending on provider policy.
Provider
- To create world class Verification IP Solutions
- To provide expert consultancy to ASIC & SoC Design companies
- To design SOCs from Architecture to Working Silicon
- To be the leading provider of Semiconductor IP Solutions
- To be a one-stop-shop for Design and Verification
- Customer Success
- Commitment to Quality
- Quality of Products
- Quality of Engineers
- Best in class Customer Support
- Ethics and Integrity
Learn more about I2C / I3C IP core
Maximizing the Usability of Your Chip Development: Design with Flexibility for the Future
MIPI I3C v1.1 - A Conversation with Ken Foust
How to Connect Sensors with I3C
MIPI CCI over I3C: Faster Camera Control for SoC Architects
Arasan I3C PHY - Ternary vs. Non-Ternary
Frequently asked questions about I2C / I3C IP cores
What is I3C 1.1.1 Verification IP?
I3C 1.1.1 Verification IP is a I2C / I3C IP core from Truechip Solutions listed on Semi IP Hub.
How should engineers evaluate this I2C / I3C?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this I2C / I3C IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.