GF L14LLP 14nm Deskew PLL - 500MHz-2500MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
GF L12LLP 12nm Deskew PLL - 125MHz-625MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
GF L12LLP 12nm Deskew PLL - 250MHz-1250MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
GF L12LLP 12nm Deskew PLL - 500MHz-2500MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
GF L14LLP 14nm DDR DLL - 120MHz-600MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise f…
GF L14LLP 14nm DDR DLL - 160MHz-800MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise f…
GF L14LLP 14nm DDR DLL - 253MHz-1265MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise f…
GF L12LLP 12nm DDR DLL - 120MHz-600MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise f…
GF L12LLP 12nm DDR DLL - 160MHz-800MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise f…
GF L12LLP 12nm DDR DLL - 253MHz-1265MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise f…
GF L14LLP 14nm Clock Generator PLL - 125MHz-625MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
GF L14LLP 14nm Clock Generator PLL - 250MHz-1250MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
GF L14LLP 14nm Clock Generator PLL - 500MHz-2500MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
GF L12LLP 12nm Clock Generator PLL - 125MHz-625MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
GF L12LLP 12nm Clock Generator PLL - 250MHz-1250MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
GF L12LLP 12nm Clock Generator PLL - 500MHz-2500MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
4Kx8 Bits OTP (One-Time Programmable) IP, GF 22nm FDX 0.8V/1.8V Process
The AT4K8G22FDX0AA is organized as a 4K-bits by 8 one-time programmable memory.
64X1 Bits OTP (One-Time Programmable) IP, GF 22nm FDX 0.8V/1.8V Process
The AT64X1G22GN0AA is organized as a 64-bit by 1 one-time programmable (OTP).
Dual Rail SRAM Globalfoundries 22FDX
Ultra-low voltage logic designs using adaptive body biasing demand dense SRAM solutions which fully integrate in the ABB aware im…
ULP Clock-Generator - GLOBALFOUNDRIES 22FDX
ABB-enabled, All-Digital PLL clock generator for ultra-low power clocking in energy efficient Systems on Chip The Ultra-Low Volta…