Fibre Channel Synthesizable Transactor
The FC Synthesizable Transactor is compliant with FC-FS-4, Rev 0.40.
Overview
The FC Synthesizable Transactor is compliant with FC-FS-4, Rev 0.40. specifications and verifies FC interfaces. Fibre Channel is build on top of it to make it robust. Fibre Channel Synthesizable Transactor provides a smart way to verify the FC component of a SOC or a ASIC in Emulator or FPGA platform. FC Synthesizable Transactor is developed by experts in networking, who have developed networking products in companies like Intel, Cortina-Systems, Emulex, Cisco. We know what it takes to verify a networking product.
Key features
- Compliant with the Fibre Channel framing and signaling specification FC-FS-6, Rev 0.1.
- Compliant with the Fibre Channel link service specification FC-LS-4, Rev 4.03.
- Compliant with the Fibre Channel physical interface specification FC-PI-7, Rev 0.13.
- Compliant with the Fibre Channel protocol for SCSI specification FCP-4.
- Compliant with SCSI Architecture Model 3/4/5 (SAM-3/4/5).
- Supports following interfaces
- 1 bit (serial) and 8,10,20,32,40,64 bit (parallel)
- 8B/10B,64B/66B,256B/257B Encoder/Decoder interface
- 32 bit Dword Primitive interface
- Dword level transport interface
- Complete Frame transaction level interface
- Supports 256GFC, 128GFC, 64GFC, 32GFC, 16GFC, 8GFC, 4GFC, 2GFC and 1GFC.
- Supports speed switching/negotiation.
- Supports L, N, and F ports.
- Supports multiple initiators and multiple targets.
- Supports generation of all types of FC frames.
- Supports verification of all layers of Fibre Channel.
- Supports Port/Process/Fabric Login/Logout.
- Supports Transmitter training.
- Supports Forward Error Correction (FEC).
- Supports Energy Efficient Fibre Channel.
- Supports all SCSI commands.
- Supports multiple outstanding exchanges.
- Supports several queuing attribute models.
- Supports Multiple Logical Unit Number (LUN) addressing.
- Supports completely configurable target/device discovery.
- Supports error detection and recovery management.
- Supports all type of FC timers.
- Supports error injection and detection at each layer
- Invalid frame fields
- Invalid EOF and SOF
- Oversize and undersize frames
- Disparity errors
- Invalid code group errors
- Invalid K and D character
- CRC error.
- Supports Retry control.
- Proficiency to generate random frames and respond to frames in directed or randomized fashion.
- Rich set of configuration parameters to control Fibre Channel functionality.
- Monitors, detects and notifies the test bench of all protocol and timing errors.
- Status counters for various events.
- Fibre Channel Verification IP comes with complete test suite to test every feature of Fibre Channel specification.
Block Diagram
Benefits
- Compatible with testbench writing using SmartDV's VIP
- All UVM sequences/testcases written with VIP can be reused
- Runs in every major emulators environment
- Runs in custom FPGA platforms
What’s Included?
- Synthesizable transactors
- Complete regression suite containing all the FC testcases
- Examples showing how to connect various components, and usage of Synthesizable Transactor
- Detailed documentation of all DPI, class, task and functions used in verification env
- Documentation contains User's Guide and Release notes
Specifications
Identity
Files
Note: some files may require an NDA depending on provider policy.
Provider
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Frequently asked questions about Fibre Channel IP cores
What is Fibre Channel Synthesizable Transactor?
Fibre Channel Synthesizable Transactor is a Fibre Channel IP core from SmartDV Technologies listed on Semi IP Hub.
How should engineers evaluate this Fibre Channel?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Fibre Channel IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.