eSPI (Enhanced Serial Peripheral Interface) Verification IP

eSPI (Enhanced Serial Peripheral Interface) is the serial synchronous communication protocol. It includes an extensive test suite covering most of the possible scenarios. It performs all possible protocol tests in a directed or a highly randomized fashion which adds the possibility to create the widest range of scenarios to verify the DUT effectively. It can work with Verilog HDL environment and works with all Verilog simulators that are support SystemVerilog.

eSPI (Enhanced Serial Peripheral Interface) Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

eSPI (Enhanced Serial Peripheral Interface) Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

• Follows eSPI basic specification as defined in Enhanced Serial Peripheral Interface (eSPI) Specification rev.1.0.
• Supports Master and Slave Mode.
• Supports 2 or 4 wire interfaces.
• Supports data width upto 8 bits.
• Supports baud rate selection.
• Supports below transaction phases
• Command Phase
• Turn-Around Phase
• Response Phase
• Supports Slave triggered transaction.
• Supports Power management Event.
• Supports In-band reset.
• Supports Interrupts and Alert.
• Supports below multiple channels
• Peripheral Channel
• Virtual Wires Channel
• Run-time Flash Access Channel
• OOB Message(Tunneled SMBus) channel
• Various kind of Master and Slave errors detection and handling
• Master detected errors
• Invalid Response Code
• Invalid Cycle Type
• Response phase CRC Error
• Malformed Packet during Response Phase
• Unsupported Cycle Type
• Unsupported Message Code
• Unsupported Length
• Unsupported Address/Length alignment
• Out of Range Address/Length combination
• Slave detected errors
• Invalid Command Opcode
• Invalid Cycle Type
• Command phase CRC Error
• Unexpected deassertion of Chip Select
• Protocol Error
• Malformed Packet during Command Phase
• Unsupported Command
• Unsupported Cycle Type
• Unsupported Message Code
• Supports CRC checking.
• Supports constraints Randomization.
• Supports backdoor initialization of data.
• Built in functional coverage analysis.
• Supports single, dual and quad mode of operation.
• Supports Callbacks in Master, Slave and Monitor for various events.
• eSPI Slave can be configured as standard device or can use FIFO for data passing.
• Master contains rich set of commands for both standard device and FIFO model mode.

• Faster testbench development and more complete verification of eSPI designs.
• Easy to use command interface simplifies testbench control and configuration of Slave and Master.
• Simplifies results analysis.
• Runs in every major simulation environment.

• Complete regression suite containing all the eSPI testcases.
• Examples showing how to connect various components and usage of Master, Slave and Monitor.
• Detailed documentation of all classes, tasks and functions used in verification env.
• Documentation contains User's Guide and Release notes.