eSPI (Enhanced Serial Peripheral Interface) Assertion IP

eSPI (Enhanced Serial Peripheral Interface) Assertion IP provides an efficient and smart way to verify the eSPI designs quickly without a testbench. The SmartDV's eSPI Assertion IP is fully compliant with standard eSPI Specification and provides the following features.

eSPI (Enhanced Serial Peripheral Interface) Assertion IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

eSPI (Enhanced Serial Peripheral Interface) Assertion IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

• Specification Compliance
• Follows eSPI basic specification as defined in Enhanced Serial Peripheral Interface(eSPI) Specification rev.1.0.
• Supports Master and Slave Mode.
• Supports 2 or 4 wire interfaces.
• Supports data width upto 8 bits.
• Supports baud rate selection.
• Supports below transaction phases
• Command Phase
• Turn-Around Phase
• Response Phase
• Supports Slave triggered transaction.
• Supports Power management Event.
• Supports In-band reset
• Supports Interrupts and Alert
• Supports below multiple channels.
• Peripheral Channel
• Virtual Wires Channel
• Run-time Flash Access Channel
• Supports CRC checking.
• Supports single, dual and quad mode of operation
• Assertion IP features
• Assertion IP includes:
• System Verilog assertions
• System Verilog assumptions
• System Verilog cover properties
• Synthesizable Verilog Auxiliary code
• Support Master mode, Slave mode, Monitor mode and Constraint mode.
• Supports Simulation mode (stimulus from SmartDV eSPI VIP) and Formal mode (stimulus from Formal tool).
• Rich set of parameters to configure eSPI Assertion IP functionality.

• Runs in every major formal and simulation environment.

• Detailed documentation of Assertion IP usage.
• Documentation also contains User's Guide and Release notes.