Vendor: T2M GmbH Category: ADC

Dual core I & Q Analog to Digital Converter

This is a dual core I & Q Analog to Digital Converter based on the Time Interleaved SAR architecture.

Overview

This is a dual core I & Q Analog to Digital Converter based on the Time Interleaved SAR architecture. The IP includes a power supply regulator (LDO), integrated references and digital compensation (for gain, offset and skew). It works in a differential mode for analog input I & Q. The output data are organized in 12x12b–buses clocked at 135MHz (Fs/12). Each bus gives the data coming from a specific sub-ADC. A data ready clock is provided at 135MHz (Fs/12).The input buffers I & Q and the LDO are in G02.The Core ADC and the Digital Compensation are in GO1.

Key features

  • Maturity MAT05
  • 9-bits DUAL-CORE I & Q SAR ADC
  • Up to 1.62Gsps Sampling Rate
  • Analog power supply for Input Buffer: from 1.7V to 2.75V (GO2 domain)
  • Analog power supply for LDO: from 1.7V to 2.75V (GO2 domain)
  • Digital power supply for Data Demux and Digital Compensation: 1.1V (GO1 domain)
  • Input range: 1 Vpp differential for I&Q
  • AC coupling input
  • Input signal bandwidth: 100Hz to 600MHz
  • Power down mode
  • Data ready output at 135MHz
  • Size: Under NDA
  • Power Consumption:
  • Analog: 68mA on GO2 supply
  • Digital Compensation: 36 mA on GO1 supply
  • Technology: under NDA
  • Device types: SVT, LVT, XHPA, GO2 (50Ang; 2.5V), MIM5f Capacitor

Block Diagram

9-Bit Dual Core SAR ADC block diagram

What’s Included?

  • Detailed Specification and Integration guide
  • LEF abstract
  • GDSII layout and Mapping files
  • LVS compatible netlist
  • Verilog-A Model

Specifications

Identity

Part Number
9-Bit Dual Core SAR ADC
Vendor
T2M GmbH
Type
Silicon IP

Provider

T2M GmbH
HQ: Germany

Learn more about ADC IP core

Frequently asked questions about ADC IP cores

What is Dual core I & Q Analog to Digital Converter?

Dual core I & Q Analog to Digital Converter is a ADC IP core from T2M GmbH listed on Semi IP Hub.

How should engineers evaluate this ADC?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this ADC IP.

Can this semiconductor IP be compared with similar products?

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