Vendor: Synopsys, Inc. Category: Temperature Sensor

Distributed Thermal Sensor (DTS) Non-Deep NWELL, TSMC N5

The granular DTS offers a significant area reduction in comparison to some standard in-chip thermal sensor solutions and supports…

Overview

The highly granular DTS offers a significant area reduction in comparison to some standard in-chip thermal sensor solutions and supports high accuracy measurement across a wide temperature range at enhanced conversion speeds. Thermal activity can be unpredictable and if not monitored carefully can cause over-heating and excessive power consumption which in turn impacts device longevity. The ability to make precise thermal measurements beside or within CPU cores, high speed interfaces or highly active circuitry has become a mandatory requirement for devices used within a range of application areas. This In-Chip Sensing and PVT Monitoring IP is available as part of the Synopsys DesignWare® Foundation IP portfolio. It also forms the foundation of the new Synopsys Silicon Lifecycle Management (SLM) platform. SLM enables new levels of insight for both SoC providers as well as their customers to optimize operational activities at each stage of the device and system lifecycles from design to in-field.

Key features

  • Small remote sensors
  • Central hub
  • High Accuracy
  • High Resolution
  • Faster conversion speed
  • Distributed Instance
  • Easily integrated
  • Digital Interface
  • Low Power

Benefits

  • Easier integration closer to hotspots in multi core devices
  • Real-time thermal mapping
  • Accurate sensing for fine grain thermal management
  • Fast, low latency conversions
  • Development of thermal and power aware silicon software
  • Supporting DVFS and AVS schemes for precise thermal management

Applications

  • Deeply embedded thermal analysis
  • DVFS
  • Thermal profiling

What’s Included?

  • GDSII
  • LEF (Abstract) view
  • Liberty timing files
  • LVS netlist
  • Verilog model

Specifications

Identity

Part Number
dwc_sensors_dts_nondeep_nwell_tsmcn5
Vendor
Synopsys, Inc.
Type
Silicon IP

Provider

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Frequently asked questions about Temperature Sensor IP cores

What is Distributed Thermal Sensor (DTS) Non-Deep NWELL, TSMC N5?

Distributed Thermal Sensor (DTS) Non-Deep NWELL, TSMC N5 is a Temperature Sensor IP core from Synopsys, Inc. listed on Semi IP Hub.

How should engineers evaluate this Temperature Sensor?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Temperature Sensor IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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