Vendor: T2M GmbH Category: LPDDR

DDR3L/ LPDDR4/ DDR4 PHY IP - 1866Mbps (Silicon Proven in UMC 28HPC+)

The DDR3L/ DDR4/ LPDDR4 Combo PHY IP offers low latency and supports throughput of up to 1866Mbps.

Controller + PHY + 1 LPDDR4 UMC 28nm HPC In Production View all specifications

Overview

The DDR3L/ DDR4/ LPDDR4 Combo PHY IP offers low latency and supports throughput of up to 1866Mbps. The PHY IP is silicon validated in the UMC 28HPC+ process technology, complies with the most recent JEDEC requirements, is used to control DRAM devices, to access the data stored in these devices, provide SSTL135, POD12 and LVSTL interfaces for DDR3L, DDR4 and LPDDR4.

Key features

  • Supported DRAM type: DDR3L/DDR4/LPDDR4
  • Maximum controller clock frequency of 400MHz resulting in maximum DRAM data rate of 1866Mbps
  • Interface: SSTL135/POD12/LVSTL
  • Data path width scales in 32-bit increment
  • Four modules for flexible configuration:CA/DQ_X16/DQ_X8/ZQ
  • Programmable output impedance (DS)
  • Programmable on-die termination (ODT)
  • Core power:0.9V, I/O power (VDDQ):1.5V/1.35V/1.2V, RX power:1.8V
  • ESD: 2KV/HBM, 200V/MM, 500V/CDM
  • Support ZQ calibration
  • Support 8 ranks
  • Support write-leveling, CBT
  • Support PHY internal VREFDQ auto decision
  • Per-bit deskew in read and write datapath
  • Silicon Proven in UMC 28HPC+ process technology
  • Supported metal scheme: 1P7M_1C

Block Diagram

DDR3L/ LPDDR4/ DDR4 Memory PHY IP in 28HPCP block diagram

What’s Included?

  • Application Note / User Manual
  • Behavior model, and protected RTL codes
  • Protected Post layout netlist and Standard Delay Format (SDF)
  • Frame view (LEF)
  • Metal GDS (GDSII)
  • Test patterns and Test Documentation

Silicon Options

Foundry Node Process Maturity
UMC 28nm HPC In Production

Specifications

Identity

Part Number
DDR3L/ LPDDR4/ DDR4 Memory PHY IP in 28HPCP
Vendor
T2M GmbH
Type
Silicon IP
Controller / PHY
Controller + PHY , PHY

Standards & Interfaces

Memory
LPDDR4

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

T2M GmbH
HQ: Germany

Learn more about LPDDR IP core

Frequently asked questions about LPDDR Interface IP

What is DDR3L/ LPDDR4/ DDR4 PHY IP - 1866Mbps (Silicon Proven in UMC 28HPC+)?

DDR3L/ LPDDR4/ DDR4 PHY IP - 1866Mbps (Silicon Proven in UMC 28HPC+) is a LPDDR IP core from T2M GmbH listed on Semi IP Hub. It is listed with support for umc In Production.

How should engineers evaluate this LPDDR?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this LPDDR IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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