Overview
The DDR3L/ DDR4/ LPDDR4 Combo PHY IP offers low latency and supports throughput of up to 1866Mbps. The PHY IP is silicon validated in the UMC 28HPC+ process technology, complies with the most recent JEDEC requirements, is used to control DRAM devices, to access the data stored in these devices, provide SSTL135, POD12 and LVSTL interfaces for DDR3L, DDR4 and LPDDR4.
Learn more about LPDDR IP core
JEDEC has just released the LPDDR6 specification that is expected to take the LPDDR DRAM market to new heights with data transfer speeds that can reach up to 14.4Gbps, which is a 50% improvement over LPDDR5X speeds. LPDDR6 device density can range from 4 GB to 64 GB.
Next-generation automotive systems are advancing beyond the limits of currently available technologies. The addition of advanced driver assistance systems (ADAS) and other advanced features requires greater processing power and increased connectivity throughout the vehicle.
As AI workloads continue to diversify, the systems that support them are evolving just as quickly. AI is no longer confined to the hyperscale data center. It is moving to the factory floor, into vehicles, and increasingly to the edge, where power, cost, and form factor constraints can matter just as much as raw performance.
Small Outline Compression-Attached Memory Module (SOCAMM) has made its way into the data center as an alternative to external CPU memory, due to its high performance, low power, memory capacity, and scalability.
This post provides an in-depth look at the fundamentals of high-speed interconnects, AI/HPC trends (HBM/D2D/CPO), and the three critical requirements of Physical AI: Deterministic Latency, Functional Safety (ISO 26262), and Automotive Reliability (AEC-Q100).
