How PCI Express Gives AI Accelerators a Super-Fast Jolt of Throughput
Madhumita Sanyal, Synopsys
Vendor:
Synopsys, Inc.
Category:
PCI Express
Configurable controllers for PCIe 4.0 supporting Endpoint, Root Complex, Switch Port, and Dual Mode applications
The silicon-proven Synopsys IP solution, consisting of configurable digital controllers, PHYs, Integrity and Data Encryption (IDE…
Overview
The complete silicon-proven Synopsys IP solution, consisting of configurable digital controllers, PHYs, Integrity and Data Encryption (IDE) Security Modules, IP Prototyping Kits and verification IP, is designed to meet all required features of the PCI Express® (PCIe®) 6.0, 5.0, 4.0, 3.1, 2.1, 1.1, and PIPE specifications. By providing a complete IP solution, Synopsys delivers
optimization across the individual IP to lower latency and ensures that all the IP functions seamlessly together to lower integration risk. The high-performance PCI Express IP solution is optimized for low power, small area and low latency.
The high-quality IP solution has been extensively validated with multiple hardware platforms, PHYs, and PCIe verification suites across a broad range of processes and foundries. With thousands of design wins and products shipping in volume, Synopsys’ expertise in developing and supporting the PCI Express interface enables designers to accelerate time-to-market and achieve silicon success for their advanced SoCs.
optimization across the individual IP to lower latency and ensures that all the IP functions seamlessly together to lower integration risk. The high-performance PCI Express IP solution is optimized for low power, small area and low latency.
The high-quality IP solution has been extensively validated with multiple hardware platforms, PHYs, and PCIe verification suites across a broad range of processes and foundries. With thousands of design wins and products shipping in volume, Synopsys’ expertise in developing and supporting the PCI Express interface enables designers to accelerate time-to-market and achieve silicon success for their advanced SoCs.
Key features
- Available in all port types including: Endpoint, Embedded Endpoint, Root Complex, Switch Port, Bridge, Dual Mode (Endpoint/Root Complex), and Multi-Port Switch
- Full Transaction Layer, Data Link Layer and Physical Layer
- Supports up to sixteen 64.0, 32.0, 16.0, 8.0, 5.0, 2.5 GT/s lanes
- Available in 32-, 64-, 128-, 256-, 512- or 1024-bit datapath widths for maximum flexibility
- 125 MHz, 250 MHz, 500 MHz, 1GHz operation
- Supports PIPE PHY 8-, 16-, 32-, 64/80-bit interface including variable clock and variable data
- Application interfaces include the Synopsys native interface or the optional Arm AMBA 5 AXI, 4 AXI and 3 AXI application interface
- Optional embedded HyperDMA™ controller with up to 64 read and 64 write channels plus descriptor pre-fetch for high throughput with minimal SoC resource overhead
- Configurable and efficient retry buffer design for low latency and area
- Supports automatic lane reversal and polarity inversion
- Supports L1 sub-states and power gating for low-power consumption
- RAS data protection providing ECC and/or Parity protection for internal busses and memories
- Advanced debug capabilities for error injection and statistical monitoring
- Ultra-low transmit and receive latency and high accessible bandwidth
- Validated with Synopsys and third-party PHYs and verification IP
- Supports up to 8 virtual channels and up to 8 traffic classes
- Directly supports up to 32 physical functions and up to 256 virtual functions using SR-IOV and ARI – Optional extension up to 64K Virtual Functions
Benefits
- Designed to meet all required features of the PCI Express 6.0 (64 GT/s), 5.0 (32
- GT/s), 4.0 (16 GT/s), 3.1 (8 GT/s), 2.1
- (5 GT/s) and 1.1 (2.5 GT/s), and PIPE specifications
- Comprehensive suite of configurable controllers for Endpoint, Embedded Endpoint, Root Complex, Switch Port, Bridge, Dual Mode, and Multi-Port Switch applications
- Optimized for low power, small area and low latency
- PHYs include advanced built-in diagnostics, enabling at-speed production testing on low-cost digital tester
- Automotive Safety Integrity Level (ASIL) B Ready ISO 26262 certified controller and PHY IP
- Built-in applications in the verification IP accelerate testbench development
- Standards-compliant Synopsys Integrity and Data Encryption Security Modules protect data transfer and are pre-verified with Synopsys Controller IP for PCI Express for fast integration and low risk
Applications
- Enterprise computing, storage area networks, networking switches, and routers
- Wireless and mobile devices
- Industrial, automotive, and IoT
- Embedded systems and set-top boxes
- Graphics devices
- Desktops, laptops, workstations, and servers
What’s Included?
- The coreConsultant utility to guide designers through the installation configuration, architectural exploration, verification, and implementation of the IP
- Verilog RTL code
- Example PHY interfaces
- ASIC and FPGA synthesis scripts
- Verification environment
- Synopsys Verification IP for the PCI Express
- Documentation: release notes, installation/integration guide, application notes, user manual
Specifications
Identity
Part Number
dwc_pci_express_4_controller
Vendor
Synopsys, Inc.
Type
Silicon IP
Standards & Interfaces
PCIe Version
PCIe 4.0
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
Learn more about PCI Express IP core
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This paper will begin with a quick overview of the specification and its application space, and then go into details such as bandwidth and clocking considerations, PHY interface differences, power management impacts, and the tradeoffs related to choices around link-layer changes. These changes may impact the transaction and application layers of devices moving from PCIe to M-PCIe, and the paper will detail those issues. A basic understanding of PCI Express concepts is helpful but not required.
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This paper discusses the integration and system verification challenges encountered when integrating a PCI Express digital intellectual property (IP) core into a Gigabit Ethernet design
Achieving Compliance and Interoperability for Your PCI Express Design
This article discusses the road to achieving compliance and the role that Synopsys DesignWare Intellectual Property (IP) for PCI Express can play in helping to achieve interoperability and compliance
Selecting PCI Express IP for Your Design
This application note provides you with a very brief introduction to the emerging PCI Express protocol and explains how selecting the right digital and mixed signal IP can accelerate the implemention of this new standard into your designs.
Frequently asked questions about PCIe IP cores
What is Configurable controllers for PCIe 4.0 supporting Endpoint, Root Complex, Switch Port, and Dual Mode applications?
Configurable controllers for PCIe 4.0 supporting Endpoint, Root Complex, Switch Port, and Dual Mode applications is a PCI Express IP core from Synopsys, Inc. listed on Semi IP Hub.
How should engineers evaluate this PCI Express?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PCI Express IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.