Vendor: Analog Bits Inc. Category: Power On Reset (POR)

Automotive Grade 1 – Power On Reset on GLOBALFOUNDRIES 22FDX-AG1

The Power-On Reset (POR) and Over Current Detection (OCD) macro comprehensively addresses typical SOC start-up power supply monit…

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GlobalFoundries 22nm FDX View all specifications

Overview

The Power-On Reset (POR) and Over Current Detection (OCD) macro comprehensively addresses typical SOC start-up power supply monitoring needs and over current detection capability, in a fully integrated easy-to-use macro. The POR includes an internal bandgap style voltage reference circuit which is used as a reference to compare the power supplies against. The POR further includes its own timebase reference circuit, so requires no clock or other synchronizing signal to work correctly. Only when both IO and Core power supplies have both exceeded a user-selected voltage level for a user-selected time, will the outputs signal that power is good.

The POR provides outputs at both the IO and core logic levels, with a low level representing a poor or unstable power supply, and a high level representing a good stable power supply. These signals may be used as logical “RSB” or “ENA” signals.

The OCD feature is a Voltage Comparator for Over Current Detection application. Ithas an integrated low- power Bandgap reference and programmable hysteresis levels. The OCD outputs will flag an output High in response to detecting an external voltage higher than the internal reference, plus a selected hysteresis amount.

Key features

  • Integrated voltage and time references for precision stand-alone operation
  • Easy to integrate with no additional component or special power requirements
  • Easy to use and configure
  • Programmable hysteresis, with independent programming available for power-on and power-off levels,
  • Programmable delay feature to assure power supply settling
  • Voltage Comparator for Over Current Detection application, with programmable hysteresis
  • Low power
  • Implemented with Analog Bits’ proprietary architecture
  • Requires no additional on-chip components, minimizing power consumption
  • Designed for Automotive (AEC-Q100) Grade 2 and Grade 1 operation

Block Diagram

Automotive Grade 1 – Power On Reset on GLOBALFOUNDRIES 22FDX-AG1 block diagram

Silicon Options

Foundry Node Process Maturity
GlobalFoundries 22nm FDX —

Specifications

Identity

Part Number
Automotive Grade 1 – Power On Reset on GLOBALFOUNDRIES 22FDX-AG1
Vendor
Analog Bits Inc.
Type
Silicon IP

Files

Product Sheet Download

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Provider

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Learn more about Power On Reset (POR) IP core

Method for Booting ARM Based Multi-Core SoCs

In the boot process various modules/peripherals (like clock controller or security handing module and other master/slaves) initialized as per the SoC architecture and customer applications. In Multi core SoCs, first primary core (also called booting core) start up in boot process and then secondary cores are enabled by software.

Analysis of RDC Paths for a million gate SoC

Reset is necessary to initialize the system and reach to a known state. Just like multiple clocks are required in an SoC to sustain various use models and performance, multiple resets are designed to cater different functional requirements. With this advent we also invite some issues due to crossings among different reset domains. In a sequential design, if the reset of source register is different from the reset of destination register even though the data path is in same clock domain, this will become asynchronous crossing path and can cause metastability at destination register.

The silicon enigma: Bridging the gap between simulation and silicon

VLSI design teams are eagerly anticipating the full functional fab out Silicon to portray their months of hard work, on the other hand the Test teams are busy planning their functional coverage (to fill in the gaps of scan (atpg) patterns coverage holes) but more often than not, the unexpected happens and the teams are busy debugging the Si bring up for functional cases. This paper is trying to highlight the seemingly innocuous issues that occur on first few day of Si bring up and proactive steps that would help reduce these cycle.

BIST Verification at SoC level

With the increase complexity of modern day SoCs, the number of memory blocks and LBIST partitions are increasing, which is in turn making the verification efforts quite challenging. This paper highlights the key points to keep in mind while deciding the verification strategy for self-test, and what are the road-blocks in executing this “ideal” verification plan.

High Density - Low power Flip-Flop

In a current trend of SoC Design, IC’s are becoming more and more complex so the challenges of meeting all the design requirements have become increasingly difficult.

Analog Bits Builds a Road to the Future at TSMC OIP

Analog Bits discussed some of the unique challenges advanced chip and multi-die design presents. Multi-domain sensing was discussed, along with the additional challenge of non-uniform thermal distributions. Real-time monitoring is another requirement. If the face of all this, calibration complexity, voltage supply noise, and crosstalk must all be dealt with as well.

Frequently asked questions about Power-On Reset (POR) IP cores

What is Automotive Grade 1 – Power On Reset on GLOBALFOUNDRIES 22FDX-AG1?

Automotive Grade 1 – Power On Reset on GLOBALFOUNDRIES 22FDX-AG1 is a Power On Reset (POR) IP core from Analog Bits Inc. listed on Semi IP Hub. It is listed with support for globalfoundries.

How should engineers evaluate this Power On Reset (POR)?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Power On Reset (POR) IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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