Vendor: SmartDV Category: ARINC 429

ARINC 664 Verification IP

The ARINC 664 Verification IP is compliant with ARINC SPECIFICATION 664 PART 7 and verifies MAC-to-PHY and PHY-to-MAC layer inter…

Verification IP View all specifications

Overview

The ARINC 664 Verification IP is compliant with ARINC SPECIFICATION 664 PART 7 and verifies MAC-to-PHY and PHY-to-MAC layer interfaces of designs with a Ethernet interface. It can work with SystemVerilog, Vera, SystemC, E and Verilog HDL environment.The SmartDV's ARINC 664 Verification IP is fully compliant with ARINC SPECIFICATION 664 PART 7 and provides the following features

ARINC 664 Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

ARINC 664 Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key features

  • Supports IEEE 802.3 10/100 Mbit/s Full duplex Ethernet links
  • Supports all word structures and protocol necessary to establish bus communication as per the specs.
  • Supports simplex,twisted shielded pair data bus standard Mark.
  • Supports LRU with multiple transmitters and receivers communicating on different buses.
  • Supports Traffic shaping in accordance with Bandwidth Allocation Gap (BAG)
  • Supports the following Upper layer protocols:
    • IPV4
    • UDP
  • Supports Transmit Redundancy Controller.
  • Glitch insertion and detection
  • Supports all types of errors insertion/detection as given below:
    • LDU Sequence Number Error
    • Parity Errors
    • Word Count Errors
    • CRC Errors
    • Time Out Errors
  • Notifies the test bench of significant events such as transactions, warnings and protocol violations.
  • Status counters for various events.
  • Monitor supports detection of all protocol violations
  • Callbacks in Transmitter and Receiver for various events
  • Built in functional coverage analysis.
  • FIFO depth programmable.
  • ARINC 664 Verification IP comes with complete testsuite to verify each and every feature of ARINC 664 Part 7 specification.

Block Diagram

ARINC 664 VIP block diagram

Benefits

  • Faster testbench development and more complete verification of ARINC 664 designs.
  • Easy to use command interface simplifies testbench control and configuration of ARINC 664 TX and RX.
  • Simplifies results analysis.
  • Runs in every major simulation environment.

What’s Included?

  • Complete regression suite containing all the testcases.
  • Examples showing how to connect various components, and usage of TX,RX BFM and Monitor.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation also contains User's Guide and Release notes.

Specifications

Identity

Part Number
ARINC 664 VIP
Vendor
SmartDV
Type
Verification IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

SmartDV
HQ: India

Learn more about ARINC 429 IP core

Keeping Pace with CXL Specification Revisions

As the Compute Express Link® (CXL®) specification rapidly evolves, so too must the tools and infrastructure used to verify designs built around it. Maintaining verification IP (VIP) that keeps pace with new specification revisions is no small task, particularly when dealing with major version shifts like the transition from CXL 2.0 to 3.0.

SmartDV Licenses SDIO IP Family to Ranix for V2X Products

To meet RANiX’s unique design goals, SmartDV will customize the IP to go beyond the standard SDIO functionality—thereby empowering RANiX to differentiate from their competitors. SmartDV will also provide RANiX with the requisite support and documentation to achieve ASIL certification for ISO 26262.

SmartDV Rolls Out Multi-Phase Expansion Plan

SmartDV™ Technologies, provider of flexible, customizable semiconductor design IP (intellectual property) and verification solutions, has expanded engineering operations beyond its headquarters in Bengaluru with the opening of a new office space in Coimbatore, Tamil Nadu, India.

Frequently asked questions about ARINC-429 IP cores

What is ARINC 664 Verification IP?

ARINC 664 Verification IP is a ARINC 429 IP core from SmartDV listed on Semi IP Hub.

How should engineers evaluate this ARINC 429?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this ARINC 429 IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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