ARINC 429 Synthesizable Transactor

ARINC 429 Synthesizable Transactor provides an smart way to verify the ARINC 429 component of a SOC or a ASIC in Emulator or FPGA platform. ARINC 429 Synthesizable Verification IP implements the air transport industry’s standards for the transfer of digital data between avionics systems. ARINC 429 Synthesizable Transactor provides an smart way to verify the ARINC 429 standard data transmission and control interfaces between source and sink. The SmartDV's ARINC 429 Synthesizable Transactor is fully compliant with ARINC SPECIFICATION 429 PART 1-17 and provides the following features.

• Supports ARINC SPECIFICATION 429 PART 1-17
• Supports all word structures and protocol necessary to establish bus communication as per the specs
• Supports simplex, twisted shielded pair data bus standard Mark 33 Digital Information Transfer System bus
• Supports LRU with multiple transmitters and receivers communicating on different buses
• Supports 32 bit words containing a 24 bit data portion containing the actual information, and an 8 bit label describing the data itself
• Supports Transmission rates at either a low speed 12.5 kHz or a high speed 100kHz
• Supports two speeds for data transmission
• Low speed operation 12.5 kHz, with an actual allowable range of 12 to 14.5 kHz
• High speed operation is 100 kHz
• Supports bipolar and Return-to-Zero encoding format
• Supports following data types
• Binary BNR Transmitted in fractional two's complement notation
• Binary Coded Decimal BCD Numerical subset of ISO Alphabet No. 5
• Discrete Data Combination of BNR, BCD or individual bit representation
• Maintenance Data and Acknowledgement Requires two-way communication
• Williamsburg/Buckhorn Protocol A bit-oriented protocol for file transfers
• Supports duplex or two-way communication in Maintenance Data and Acknowledgement between source and sink
• Supports glitch injection and detection
• Supports all types of errors insertion/detection as given below:
• Missing SOT word
• LDU Sequence Number Error
• Parity Errors
• Word Count Errors
• CRC Errors
• Time Out Errors

• Compatible with testbench writing using SmartDV's VIP
• All UVM sequences/testcases written with VIP can be reused
• Runs in every major emulators environment
• Runs in custom FPGA platforms

• Synthesizable transactors
• Complete regression suite containing all the ARINC 429 testcases
• Examples showing how to connect various components, and usage of Synthesiable VIP
• Detailed documentation of all DPI, class, task and functions used in verification env
• Documentation contains User's Guide and Release notes