What is APB I2C master and slave?
APB I2C master and slave is a I2C / I3C IP core from eSi-RISC listed on Semi IP Hub.
Vendor:
eSi-RISC
Category:
I2C / I3C
APB I2C master and slave
The eSi-I2C core implements the I2C two-wire protocol.
Overview
The eSi-I2C core implements the I2C two-wire protocol. It supports operation as both an I2C master and slave. The I2C is supplied with an AMBA APB slave interface and so can be driven by software or via DMA.
Key features
- Multi-master / slave operation.
- Clock stretching.
- 7 and 10-bit addresses.
- Programmable bit rate.
- Programmable digital filtering for SDA and SDL inputs.
- Configurable TX and RX FIFOs.
- AMBA 3 APB slave interface.
- DMA flow-control interface.
Block Diagram
eSi-I2C block diagram
What’s Included?
- Verilog RTL
- Testbench
- Simulation and synthesis scripts
- Documentation
- C API
Specifications
Identity
Part Number
eSi-I2C
Vendor
eSi-RISC
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
UK
Frequently asked questions about I2C / I3C IP cores
How should engineers evaluate this I2C / I3C?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this I2C / I3C IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.