AMBA ACE4-Lite Verification IP

AMBA ACE4-Lite Verification IP provides an smart way to verify the ARM AMBA ACE4-Lite component of a SOC or a ASIC. The SmartDV's AMBA ACE4-Lite Verification IP is fully compliant with standard AMBA ACE4-Lite Specification.

AMBA ACE4-Lite Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

AMBA ACE4-Lite Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

• Compliant with the latest ARM AMBA ACE4-Lite Protocol Specification.
• Supports ACE4-Lite Master, Slave, Interconnect, Monitor and Checker.
• Supports all ACE4-Lite data and address widths.
• Supports all protocol transfer types, burst types, burst lengths, burst sizes and response types.
• Supports constrained randomization of protocol attributes.
• Separate address/control, data and response phases. Separate read and write channels.
• Support for burst-based transactions with only start address issued.
• Slave, Interconnect and Master support fine grain control of response per address or per transaction.
• Programmable wait states or delay insertion on different channels. Interconnect has the ability to replicate Master/Slave inserted delays.
• Ability to inject errors during data transfer.
• Write strobe support to enable sparse data transfer on the write data bus.
• Narrow transfer support.
• Unaligned address access support.
• Ability to issue multiple outstanding transactions.
• Out of order transaction completion support.
• Protected accesses with normal/privileged,secure/non-secure and data/instruction
• Ability to configure the width of all signals.
• Support for conversion of different protocols and different data width.
• Support for bus inactivity detection and timeout.
• Configurable WID signal enable support.
• Read data interleaving support with programmable interleave depth and programmable interleave size per transaction to allow fixed and variable data interleaving in a transaction.
• Atomic access support with normal access and exclusive access
• Longer bursts up to 256 beats.
• Quality of Service signaling.
• Multiple region interfaces.
• User signaling support.
• Ability to break longer bursts into multiple shorter bursts
• Supports unmapped region address accesses
• AWCACHE and ARCACHE Attributes.
• Low-power Interface support
• ACE4-Lite specific features
• Supports functionality to verify ACE4-Lite.
• Supports all ACE4-Lite transaction types.
• Support for multiple outstanding ACE4-Lite transactions.
• Supports all write/read responses.
• Fine grain control of Initiating Master transaction including main memory access.
• Fine grain control of Interconnect generated main memory access transactions.
• Barrier transactions
• Shareable and Non-shareable transactions.
• Broadcast cache maintenance operations.
• Programmable Timeout insertion.
• Supports FIFO memory.
• Rich set of configuration parameters to control ACE4-Lite functionality.
• On-the-fly protocol and data checking.
• Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
• Built in coverage analysis.
• Callbacks in Master, Slave, Interconnect and Monitor for various events.
• Status counters for various events on bus.
• ACE4-Lite Verification IP comes with complete testsuite to test every feature of ARM AMBA ACE4-Lite specification.

• Faster testbench development and more complete verification of AMBA ACE4-Lite designs.
• Easy to use command interface simplifies testbench control and configuration of Master, Slave and Interconnect.
• Simplifies results analysis.
• Runs in every major simulation environment.

• Complete regression suite containing all the AMBA ACE4-Lite testcases.
• Examples showing how to connect various components, and usage of BFM and Monitor.
• Detailed documentation of all class, task and function's used in verification env.
• Documentation also contains User's Guide and Release notes.