Vendor: T2M GmbH Category: Symmetric Crypto

Advanced Encryption Standard compliant with FIPS 197

AES bridge, a cryptographic coprocessor that complies with FIPS 197 Encryption Standard, employs the Rijndael encryption method t…

Overview

AES bridge, a cryptographic coprocessor that complies with FIPS 197 Advanced Encryption Standard, employs the Rijndael encryption method to link APB, AHB, and AXI bus.

AES is a block cipher that is frequently used in security solutions, ranging from cloud servers to IoT devices. Performance and security are much improved when it is implemented in hardware as opposed to software.

Key features

  • Support for 128 and 256 key bit length
  • Support for ECB, CBC, CFB, OFB, CTR block cipher modes
  • Internal key expansion module
  • Flexible data read/write modes
  • Available system interface wrappers:
  • AMBA – APB / AHB / AXI Bus
  • Altera Avalon Bus
  • Xilinx OPB Bus

Benefits

  • Digital signature
  • Data integrity
  • Key derivation
  • TLS/SSH/PGP IPsec communication

What’s Included?

  • Source Code:
  • VERILOG test bench environment
  • Technical documentation
  • Synthesis scripts
  • Example application
  • Technical support

Specifications

Identity

Part Number
AES IP Core
Vendor
T2M GmbH
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

T2M GmbH
HQ: Germany

Learn more about Symmetric Crypto IP core

Frequently asked questions about Symmetric Cryptography IP cores

What is Advanced Encryption Standard compliant with FIPS 197?

Advanced Encryption Standard compliant with FIPS 197 is a Symmetric Crypto IP core from T2M GmbH listed on Semi IP Hub.

How should engineers evaluate this Symmetric Crypto?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Symmetric Crypto IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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