CDM Dependence on Device Capacitance
This blog will focus on what happens during the CDM pulse itself, and will show how the pulse properties change as a function of DUT to Field Plate capacitance.
Vendor:
Certus Semiconductor
Category:
Oscillator
A 28nm 1.8V-3.3V Fail-Safe General-Purpose IO & OSC
This 28nm GPIO is designed for high-speed (>150MHz output, >250MHz input) applications.
Overview
This 28nm GPIO is designed for high-speed (>150MHz output, >250MHz input) applications. The IO operates at either 1.8V or 3.3V and can dynamically switch between these voltages during operation. The cell is power sequence-independent and is fully self-protecting during the power ramp. A unique feature of the 28nm GPIO is its fail-safe capability. Though a full push-pull IO, the part can be powered down and leak low current from externally driven active signals, much like an open-drain IO.
Built into our IO libraries and also offered as a separate service is our strong ESD expertise. Certus was founded by ESD engineers, and our results speak for themselves. We consistently exceed 2KV HBM and 500V CDM ESD targets and provide on-chip solutions for standards such as IEC-61000-4-2, system-level ESD, and Cable Discharge Events (CDE).
Certus supports IO libraries across multiple TSMC nodes, including 180nm, 130nm, 40nm, 28nm, 22nm, and 16/12nm. Certus is particularly suited at providing custom variants in a cost-efficient framework. Please contact us for supplementary physical or electrical features that can suit your needs.
Built into our IO libraries and also offered as a separate service is our strong ESD expertise. Certus was founded by ESD engineers, and our results speak for themselves. We consistently exceed 2KV HBM and 500V CDM ESD targets and provide on-chip solutions for standards such as IEC-61000-4-2, system-level ESD, and Cable Discharge Events (CDE).
Certus supports IO libraries across multiple TSMC nodes, including 180nm, 130nm, 40nm, 28nm, 22nm, and 16/12nm. Certus is particularly suited at providing custom variants in a cost-efficient framework. Please contact us for supplementary physical or electrical features that can suit your needs.
Key features
- Fail-Safe GPIO in TSMC 28nm process technology
- JEDEC LVCMOS compliant
- RGMII, SD capable
- 1.8V-3.3V dynamic multi-voltage operation
- Selectable drive strengths
- Selectable input hysteresis
- 20um pitch, 180um tall cell
- Triple-row staggered wirebond pad arrangement
- >2kV HBM, 500V CDM ESD
- Physical features
- 20um x 186um cell size
- 9 metals - 6X2Z
- 20um pitch, triple row staggered wirebond
- This library also features a 33MHz OSC (3.3V).
Block Diagram
28nm Fail-Safe IO Library block diagram
Benefits
- Tight cell pitch
- Small footprint triple staggered wirebond
- Fast GPIO
- Fail-Safe IO
- Power sequence independence
- Selectable input hysteresis
- Proven HBM & CDM ESD protection
Applications
- General Purpose Applications
- Memory interfaces
- Open-Drain IO applications
- RGMII
- FLASH and SD Card interfaces
- UARTS
What’s Included?
- GDS
- CDL netlist
- Verilog stub
- Verilog behavioral model
- LEF
- Liberty Timing Files
- IBIS (option)
- Electrical datasheet
- User guide and application notes
- Consulting and Support
Specifications
Identity
Part Number
28nm Fail-Safe IO Library
Vendor
Certus Semiconductor
Type
Silicon IP
Provider
HQ:
United States
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Frequently asked questions about Oscillator IP cores
What is A 28nm 1.8V-3.3V Fail-Safe General-Purpose IO & OSC?
A 28nm 1.8V-3.3V Fail-Safe General-Purpose IO & OSC is a Oscillator IP core from Certus Semiconductor listed on Semi IP Hub.
How should engineers evaluate this Oscillator?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Oscillator IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.