Vendor: Attopsemi Technology Category: eFuse / OTP

4608x12 Bits OTP (One-Time Programmable) IP, TSMC 40ULP 0.9V/2.5V Process

The ATO4608X12TS040ULP7ZA is organized as 4608 x 12 one-time programmable (OTP).

TSMC 40nm ULP Silicon Proven View all specifications

Overview

The ATO4608X12TS040ULP7ZA is organized as 4608 x 12 one-time programmable (OTP). This is a type of non-volatile memory fabricated in TSMC 40nm ULP standard CMOS core logic process. The OTP can be widely used in chip ID, security key, memory redundancy, parameter trimming, configuration setting, feature selection, and PROM, etc.

Key features

  • Fully compatible with standard TSMC 40nm ULP 0.9V/2.5V CMOS logic process
  • Low voltage: VDD 0.9 V ± 10% for read and program; VDDP: 1.71–3.60 V for read and 2.65 V ± 5% for program
  • High speed program: 10-us programming time and support up to dual-bit concurrent programming at one CLK cycle
  • High speed read: 10-MHz read clock (100-ns cycle time) per 12-bit word.
  • Asynchronous mode with output latches
  • Deep sleep by bringing VDD down to 0 V for SoC power saving
  • Built-in test mode support
  • Built-in fuse protection circuits
  • Wide temperature range: -40-125 °C read and -40-125 °C program

Benefits

  • Small IP size
  • Low program voltage/current
  • Low read voltage/current
  • High reliability
  • Silicon characterized and qualified

What’s Included?

  • Datasheet
  • Verilog behavior model and test bench
  • Timing library
  • LEF File
  • Phantom GDSII database

Silicon Options

Foundry Node Process Maturity
TSMC 40nm ULP Silicon Proven

Specifications

Identity

Part Number
ATO4608X12TS040ULP7ZA
Vendor
Attopsemi Technology
Type
Silicon IP

Provider

Learn more about eFuse / OTP IP core

I-fuse: Most Reliable and Fully Testable OTP

Patented by Attopsemi™, I-fuse™ is a revolutionary non-breaking fuse technology that can be reliably programmed by heat assisted electromigration below a break point. Any cell can be tested as programmable if the initial fuse resistance is low enough (e.g. <400 ohms) to generate enough heat for programming.

I-fuse OTP - The OTP of Choice

OTP stands for “One-Time Programmable”, a device that can only be programmed once to permanently store any kind of information (data for chip IDs, security keys, product feature selection, memory redundancy, device trimming, or MCU code memory). Every chip needs OTPs, as long as they are reliable, available, and affordable.

Frequently asked questions about eFuse / OTP IP cores

What is 4608x12 Bits OTP (One-Time Programmable) IP, TSMC 40ULP 0.9V/2.5V Process?

4608x12 Bits OTP (One-Time Programmable) IP, TSMC 40ULP 0.9V/2.5V Process is a eFuse / OTP IP core from Attopsemi Technology listed on Semi IP Hub. It is listed with support for tsmc Silicon Proven.

How should engineers evaluate this eFuse / OTP?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this eFuse / OTP IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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