What is 256-steps adjustable delay cell?
256-steps adjustable delay cell is a DLL IP core from VEGA Semiconductor listed on Semi IP Hub. It is listed with support for umc Available on request.
Vendor:
VEGA Semiconductor
Category:
DLL
256-steps adjustable delay cell
U40LPDLLDLYV1 is a 256-steps adjustable delay cell IP.
Overview
U40LPDLLDLYV1 is a 256-steps adjustable delay cell IP. It is based on UMC 40nm low power process.
Key features
- Process: UMC 40nm Logic and Mixed-Mode 2.5V/1.1V Low Power Process
- Adjustable 8-bit delay steps, Maximum delay time 25.5ns, and Minimum delay time = 0.1ns (resolution: 0.1ns).
- Power Supply: Core power supply 1.1V
- Area : 600um ^2
Block Diagram
U40LPDLLDLYV1 block diagram
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| UMC | 40nm | 40nm 400 nm | Available on request |
Specifications
Identity
Part Number
U40LPDLLDLYV1
Vendor
VEGA Semiconductor
Type
Silicon IP
Provider
HQ:
Taiwan
Frequently asked questions about DLL IP cores
How should engineers evaluate this DLL?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DLL IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.