24-bit/-140 dB THD+N Multi-Channel Audio Async Sample Rate Converter

The IObundle 24-bit/-130dB THD+N Multi-Channel Audio Asynchronous Sample Rate Converter resamples the input audio digital signal, sampled at frequency Fin, and produces an output signal, sampled at frequency Fout . It uses a variable-coefficient FIR filter, a ratio estimator module to compute the conversion ratio ? = F out /F in and its inverse 1/?, a
ROM&Interpolation module to compute the filter coefficients, a circular RAM block to store the input samples and an output FIFO to store the output samples. The FIR filter has order 32 for up conversions and 32/? for down conversions. Conversions between any two frequencies in the [8, 192] kHz range have been exhaustively tested. The design uses three clock domains. The input and output word clocks are asynchronously sampled to compute their periods and
therefore ? and 1/?. All computation is performed in the system clock domain. The core can process tens to hundreds of Time-Division Multiplexed (TDM) audio channels, depending on the system clock frequency. The output group delay variation upon reset is less than one output sample period. The Total Harmonic Distortion plus Noise (THD+N) has an average of -140dB and is never higher than -130dB. TheseTHD+N values are achieved after a fixed sync time of 20 ms.

• Achieves very low THD+N: average -140dB, maximum -130dB
• 20 ms seconds sync time after reset (for computing the conversion ratio)
• Supports tens to hundreds of audio TDM channels, depending on the system clock frequency
• Supports conversion ratios from 1:24 to 24:1
• Simple audio input and output streaming interfaces.
• Less than 1 output sample period group delay variation after reset

• Compact hardware implementation with low power consumption: can fit many instances in low-cost FPGAs and ASICs
• Very low THD+N, fast sync time, ample conversion ratio range, single-sample group delay after reset
• Tens to hundreds of TDM audio channels processed without any extra latency or hardware overhead

• Broadcasting
• High fidelity consumer audio

• RTL code or netlist in Verilog for ASIC and FPGA
• RTL testbench
• ASIC synthesis and place and route scripts and constraints
• Comprehensive user and system integration documentation