17nA Current Bias with Enable Low Voltage (1.0V), Ultra Low Power (90nW @ 1.8V)
This macro-cell is a low power general purpose current bias generator core designed for TowerJazz 0.18µm TS18SL CMOS technology.
Overview
This macro-cell is a low power general purpose current bias generator core designed for TowerJazz 0.18µm TS18SL CMOS technology.
The circuit generates 2 × NMOS 17nA current branches. The current bias is temperature compensated.
Output currents come from NMOS drain terminals, thus being sink-type sources.
Key features
- Low power current bias
- Low TC
- Ibias=17nA ±12% (without trimming)
- Current consumption lower than 61nA in active mode
- Flexible voltage operation: 1.0V–2.0V
- Enable control
- Indicative area: 0.0037mm2
Block Diagram
Applications
- Passive/active RFID tag ICs
- Portable devices
- Energy Harvesting ICs
- Hearing Aids
What’s Included?
- Datasheet/Integration Guide
- HDL Model
- Flat GDSII database/LVS netlist
- Customer Support
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| Tower | 180nm | SL | Silicon Proven |
Specifications
Identity
Files
Note: some files may require an NDA depending on provider policy.
Provider
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Frequently asked questions about Voltage Reference IP cores
What is 17nA Current Bias with Enable Low Voltage (1.0V), Ultra Low Power (90nW @ 1.8V)?
17nA Current Bias with Enable Low Voltage (1.0V), Ultra Low Power (90nW @ 1.8V) is a Voltage Reference IP core from Chipus Microelectronics listed on Semi IP Hub. It is listed with support for tower Silicon Proven.
How should engineers evaluate this Voltage Reference?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Voltage Reference IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.