Overview
Our analog-to-digital converter is a configurationally general-purpose ADC that uses a traditional Charge-Redistribution SAR architecture referenced to VDD, VSS. The 10-bit ADC has an architecture of successive approximation analog to digital converter circuit. The architecture is capable of achieving up to 10-bit resolution. It includes an eight-channel input multiplexor and provides input buffers that may be bypassed for full rail-to-rail capability. Successive approximation analog to digital converter consists of four main subcircuits: sample and hold circuit to acquire the input voltage (Vin), analog voltage comparator that compares Vin to the output of the internal DAC and outputs the result of the comparison to the successive approximation logic.The ADC does not require any special analog options and can be cost-effectively ported across foundries and process nodes upon request.Our analog-to-digital converter can be tuned to your specifications and is ideally suited for signal conversion and monitoring in applications such as in IoT, Security, Automotive, AI and general SoCs and ASICs.
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This paper introduces a novel closed-loop testing methodology for efficient linearity testing of high-resolution Successive Approximation Register (SAR) Analog-to-Digital Converters (ADCs). Existing test strategies, including histogram-based approaches, sine wave testing, and model-driven reconstruction, often rely on dense data acquisition followed by offline post-processing, which increases overall test time and complexity.
Analog to digital converters have three key input ports along with data output ports as per digital resolution requirements. These inputs ports are Analog Signal, Reference and Clock. If we compare across most of the converter architectures then clock frequency is directly related to output data rate and latency of the data conversion.
The growing availability of digital ICs like microcontrollers, microprocessors, and field-programmable gate arrays (FPGAs) allows developers to use complex digital processing techniques rather than analog signal conditioning. For this reason, analog-to-digital converters (ADCs) have become a widely-used component in mixed-signal circuits.
In high end RF systems, such as 5G radios, the requirements are so stringent that the source of this strongest unwanted tone can be the PLL. This article outlines how spurs in the input clock to the ADC or DAC may limit the SFDR. This in turn will set the requirements for the spurs for the input clock (from a PLL), in order to achieve a specific SFDR.
Power-sensitive applications such as Internet-of-Things (IoT) require a comprehensive power savings strategy within the system-on-chip (SoC). Techniques relying solely on the use of traditional power down modes and low supply voltage may not be enough to achieve the required power targets. The analog block is often assumed to be too sensitive and not compatible with aggressive power management techniques.
When continuously running a high speed ADC, it can be a challenge to deal with the firehose of raw data available at the output. To use City Semiconductor’s 2.5 GS/s 12-bit ADC, for example, 30 gigabits per second of data have to be accepted.
