10-bit, 5 MSPS ADC in 12nm CMOS on GF 12nm LP+
The ADC is an ultra-low-power ADC designed in a GF 12nm LP+ process.
Overview
The ADC is an ultra-low-power ADC designed in a GF 12nm LP+ process.
This 10-bit, 5MSPS ADC supports input signals up to 1 MHz and features 2V differential full-scale input range with excellent static and dynamic performance. The input front-end includes a 4:1 mux.
The ADC architecture is optimized to maximize performance while minimizing power and area consumption.
Key features
- Ultra-low-power, high-performance ADC
- 10-bit ADC resolution
- Sampling rate up to 5MSPS
- Differential input signal
- SNR up to 55 dB
- Selectable inputs
Block Diagram
Applications
- General Purpose Auxiliary ADC
- General purpose software defined radio
- data acquisition systems
- communications
- medical imaging
What’s Included?
- Datasheet
- Hard Macro (GDSII)
- Characterization Report (as applicable)
- Abstract View (LEF) for top level connectivity
- Spectre Netlist (as needed upon request)
- Behavioral Model
- Integration and Customer Support
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| GlobalFoundries | 12nm | LP+ | — |
Specifications
Identity
Analog
Provider
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Frequently asked questions about ADC IP cores
What is 10-bit, 5 MSPS ADC in 12nm CMOS on GF 12nm LP+?
10-bit, 5 MSPS ADC in 12nm CMOS on GF 12nm LP+ is a ADC IP core from Omni Design Technologies, Inc. listed on Semi IP Hub. It is listed with support for globalfoundries.
How should engineers evaluate this ADC?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this ADC IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.