Vendor: Actt Category: PLL

1.4GHz Frac-N PLL

This is an analog PLL frequency synthesizer, which can generate independent clock with frequency range from 25MHz to 1.4GHz.

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Overview

This is an analog PLL frequency synthesizer, which can generate independent clock with frequency range from 25MHz to 1.4GHz. It supports 4MHz to 180MHz input clock frequency range.This IP works with delta-sigma fractional-N structure. Compared with the traditional delta-sigma fractional-N analog PLL, this IP adopts an advanced loop structure, and achieves higher performance with a smaller size.

Key features

  • Analog PLL frequency synthesizer, output clock range from 25MHz to 1.4GHz
  • Delta-sigma fractional-N structure to be suitable for different kinds of applications
  • An advanced 3-order analog LP filter with more than 70% size reduction
  • An advanced 3-order delta-sigma fractional divider
  • Supports integer-N divider application
  • Duplex output clock signals, high frequency clock and low frequency clock
  • Supports 4MHz to 180MHz input clock frequency range
  • Internal high bandwidth regulator to restrain power disturbance
  • Low jitter design: (RMS jitter)
  • Integer-N divider application: <2ps@1GHz, <1.8ps@1.4GHz
  • Fractional-N divider application: <11ps@1GHz, <5ps@1.4GHz

Applications

  • SoC

Specifications

Identity

Part Number
1.4GHz Frac-N PLL
Vendor
Actt
Type
Silicon IP

Provider

Actt
HQ: China
Contact Actt

Learn more about PLL IP core

Creating a Frequency Plan for a System using a PLL

How do you ensure that every part of a system receives the clock it needs—without wasting power or sacrificing performance? The answer lies in creating a well-structured frequency plan built around a PLL.

Specifying a PLL Part 3: Jitter Budgeting for Synthesis

This white paper is aimed at system architects and physical implementation leaders working on the design of SoCs. It can be confusing to understand the impact of different jitter sources and how to calculate a jitter budget when specifying a digital system. This white paper explains how jitter changes the period of a clock and how to ensure that jitter has correctly been accounted for in the calculations for timing closure.

Specifying a PLL Part 2: Jitter Basics

This article explains a some of the key terminology and parameters commonly used to describe jitter. It will also help clarify the most important parameters for a some PLL applications, allowing the designer to better understand what is required from a PLL.

Specifying a PLL Part 1: Calculating PLL Clock Spur Requirements from ADC or DAC SFDR

In high end RF systems, such as 5G radios, the requirements are so stringent that the source of this strongest unwanted tone can be the PLL. This article outlines how spurs in the input clock to the ADC or DAC may limit the SFDR. This in turn will set the requirements for the spurs for the input clock (from a PLL), in order to achieve a specific SFDR.

Achieving Groundbreaking Performance with a Digital PLL

This article compares analog, first-generation digital, and second-generation digital PLLs. It evaluates which type of PLL may be best in which situation. It further discloses a roadmap into other application areas, including general purpose / logic clocking, and regular low-jitter PLLs.

Frequently asked questions about PLL IP cores

What is 1.4GHz Frac-N PLL?

1.4GHz Frac-N PLL is a PLL IP core from Actt listed on Semi IP Hub.

How should engineers evaluate this PLL?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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