USB3.0 PHY on GF22FDX and Samsung 28nm FDSOI
The USB3.0 PHY IP is designed according to the USB 3.0, USB2.0 Specification.
MIPI D-PHY Transmitter/Receiver for DSI/CSI-2 on Samsung 28nm FD-SOI
The Renesas MIPI D-PHY Transmitter/Receiver is useful 4 Data Channel transmitter/receiver hard macro for DSI/CSI-2 of Samsung 28n…
Samsung 28nm FDSOI MIPI DPHY V1.1
IP
Samsung 28nm FDSOI 1.8v/1.0v LVDS Transmitter
IP
Samsung 28nm FDSOI 1.8v/1.0v sub-LVDS Receiver
IP
Samsung 28nm FDSOI 1.8v/1.0v APLL
IP
Samsung 28nm FDSOI 1.8v/1.0v APLL
This IP is a programmable Analog PLL suitable for high speed clock generation.
Samsung 28nm FDSOI 1.8v/1.0v APLL
This IP is a programmable Analog PLL suitable for high speed clock generation.
Samsung 28nm FDSOI USB3.0 and PCIE2 combo PHY
The USB3.0 Super-Speed / PCI Express Combo PHY is a programmable IP that is compatible with the PHY Interface for PCI Express and…
Samsung 28nm FDSOI USB3.0 Type-C PHY
IP
The SEC28FDSOI18_CODEC_04 integrates: 2-channel 24-bit sigma-delta ADC, 2-channel 24-bit sigma-delta DAC with headphone driver am…
SAMSUNG 28nm FDSOI USB2.0 Dual Role PHY/OTG PHY
The USB 2.0 OTG PHY is a Hi-Speed USB peripheral transceiver IP that implements the Intel® UTMI standard.
The USB3.0 PHY IP is designed according to the USB 3.0, USB2.0 Specification.
Samsung 28nm Low Voltage Single-Port SRAM Compiler
VeriSilicon Samsung 28FDSOI Low Voltage Synchronous Single-Port SRAM compiler optimized for Samsung FDSOI 28nm process can flexib…
Samsung 28nm Low Power Single-Port SRAM Compiler
VeriSilicon Samsung 28FDSOI Low Power Synchronous Single-Port SRAM compiler optimized for Samsung FDSOI 28nm process can flexibly…
Adaptive Body Bias Generator on Samsung 28nm LN28FDS
The adaptive body bias generator (ABBG) consists of a positive-BBG and a negative-BBG for FDSOI-MOS transistors.