D/A Converter IP, 12 bits, 50Ksps, HJTC 0.18um eFlash/G2 process
3.3V 12-Bit 50KSPS Low Power R-2R Digital-to-Analog converter in HJTC 0.18um eFlash process.
- 12 Bit
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
D/A Converter IP, 12 bits, 50Ksps, HJTC 0.18um eFlash/G2 process
3.3V 12-Bit 50KSPS Low Power R-2R Digital-to-Analog converter in HJTC 0.18um eFlash process.
D/A Converter IP, 12 bits, 220Ksps, HJTC 0.18um eFlash process
12-Bit 200KSPS lower power R-2R Digital-to-Analog converter with core voltage level, by HJTC 0.18um eFlash process.
D/A Converter IP, 10 bits, 2.5Msps, HJTC 0.18um Logic process
10-Bit 2.5MSPS current Digital-to-Analog converter, HJ 0.18um Logic process.
Band Gap IP, Input: 2.5V - 5.5V, VBG=1.21V, HJTC 0.18um eFlash/G2 process
Input 2.5V-5.5V, VBG=1.21V bandgap, HJTC 0.18um eFlash process.
Band Gap IP, Input: 2.0V - 3.6V, VBG=1.21V, HJTC 0.18um eFlash/G2 process
Input 2.0V-3.6V, VBG=1.21V bandgap, HJTC 0.18um eFlash process.
A/D Converter IP, 11 bits, 1Msps, with 8-to-1 input MUX, HJTC 0.18um eFlash/G2 process
SAR Analog-to-Digital converter with 8-to-1 Mux and resistive touch panel driver, HJTC 0.18um 2P6M eFlash process.
A/D Converter IP, 10 bits, 500Ksps, HJTC 0.18um eFlash/G2 process
10-Bit 500KSPS SAR Analog-to-Digital converter with internal temperature sensor, HJTC 0.18um eFlash process.
A/D Converter IP, 10 bits, 1Msps, HJTC 0.18um eFlash/G2 process
10-Bit 1MSPS SAR Analog-to-Digital converter, HJTC 0.18um eFlash process.
A/D Converter IP, 10 bits, 167Ksps, HJTC 0.18um eFlash/G2 process
A 3.3V, 10-Bit 167KSPS 8-to-1 Low Power SAR Analog-to-Digital converter with internal temperature sensor, HJTC 0.18um eFlash proc…
Controller IP, System Power/Clock Management, Soft IP
The system control unit, is designed to provide a power and clock management functions for System-on-a-Chip (SoC) to handle opera…
AXI system Peripheral IP, AXI Bus System Interconnect, Soft IP
AXI bus interconnect.
Nand Flash Controller with AHB Interface over 74-Bit ECC correction capacity.
Standard Cell (High Voltage) Library IP, 9 tracks, UMC 0.162um eHV process
UMC 0.162um eHV 3.3V/8.25V/16.5V process Standard Cell Library.
Standard Cell (High Voltage) Library IP, 9 tracks, UMC 0.135um eHV process
UMC 0.135um Embedded High Voltage 1.5V Core Cell Library.
Standard Cell (Generic) Library IP, 9 tracks, UMC 0.162um eFlash process
UMC 0.162um eFlash process Generic Cell Library.
General Purpose IO IP, UMC 0.153um LL process
UMC 0.153um 3.3V IO Mixed-Mode/Logic process True 3.3V IO Cell Library (blown up version of 0.18um IO ).
General Purpose IO IP, 5V tolerance, UMC 0.153um LL process
UMC 0.153um Mixed-Mode/Logic 3.3V IO Logic process 5V Tolerant Standard IO Cell Library (blown up version of 0.18um IO).
MIPI Controller IP, CSI-2 Transmitter, High-Speed 80Mbps to 1.5Gbps per data lane, Soft IP
MIPI Transmitter Controller.
MIPI Controller IP, DSI Peripheral, Soft IP
MIPI DSI Peripheral Controller.
MIPI Controller IP, DSI Host, Soft IP
DSI Host Controller.