Standard Cell PowerSlash(TM) Library IP, HVT, 7 tracks, UMC 55nm LP process
UMC 55nm LP/HVT Low-K Logic process 7-Track POWERSLASH Cell Library.
- UMC
- 55nm
- LP
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Standard Cell PowerSlash(TM) Library IP, HVT, 7 tracks, UMC 55nm LP process
UMC 55nm LP/HVT Low-K Logic process 7-Track POWERSLASH Cell Library.
Standard Cell PowerSlash(TM) Library IP, RVT, 8 tracks, UMC 55nm LP process
UMC 55nm LP/RVT Low-K Logic process 8-Track POWERSLASH Core Cell Library.
Standard Cell PowerSlash(TM) Library IP, LVT, 8 tracks, UMC 55nm LP process
UMC 55nm LP/LVT Low-K Logic process 8-Track POWERSLASH Core Cell Library.
Standard Cell PowerSlash(TM) Library IP, HVT, 8 tracks, UMC 55nm LP process
UMC 55nm LP/HVT Low-K Logic process 8-Track POWERSLASH Core Cell Library.
Standard Cell PowerSlash(TM) Library IP, RVT, 7 tracks, UMC 40nm LP process
UMC 40nm LP/RVT Low-K Logic process 7-Track POWERSLASH Cell Library.
Standard Cell PowerSlash(TM) Library IP, RVT, 12 tracks, UMC 40nm LP process
UMC 40nm LP/RVT Logic process 12-Track high speed POWERSLASH Cell Library (C40).
Standard Cell PowerSlash(TM) Library IP, LVT, 12 tracks, UMC 40nm LP process
UMC 40nm LP/LVT Logic process 12-Track high speed POWERSLASH Core Cell Library.
Standard Cell PowerSlash(TM) Library IP, HVT, 12 tracks, UMC 40nm LP process
UMC 40nm LP/HVT Logic process 12-Track high speed Cell POWERSLASH Library (C40).
Standard Cell PowerSlash(TM) Library IP, LVT, 7 tracks, UMC 40nm LP process
UMC 40nm LP/LVT Low-K Logic process 7-Track POWERSLASH Cell Library.
Standard Cell PowerSlash(TM) Library IP, HVT, 7 tracks, UMC 40nm LP process
UMC 40nm LP/HVT Low-K Logic process 7-Track POWERSLASH Cell Library.
Standard Cell PowerSlash(TM) Library IP, RVT, 9 tracks, UMC 40nm LP process
UMC 40nm LP/RVT Logic process 9-Track Standard Cell Library (POWERSLASH Core).
Standard Cell PowerSlash(TM) Library IP, LVT, 9 tracks, UMC 40nm LP process
UMC 40nm LP/LVT Logic process 9-Track Standard Cell Library (POWERSLASH Core).
Standard Cell PowerSlash(TM) Library IP, HVT, 9 tracks, UMC 40nm LP process
UMC 40nm LP/HVT Logic process 9-Track Standard Cell Library (POWERSLASH Core).
Standard Cell PowerSlash(TM) Library IP, RVT, 12 tracks, UMC 28nm HLP process
UMC 28nm Logic and Mixed-Mode HLP/RVT process 12-Track Standard POWERSLASH Core Cell Library (C35).
Standard Cell PowerSlash(TM) Library IP, LVT, 12 tracks, UMC 28nm HLP process
UMC 28nm Logic and Mixed-Mode HLP/LVT process 12-Track POWERSLASH Cell Library (C35).
Standard Cell PowerSlash(TM) Library IP, HVT, 12 tracks, UMC 28nm HLP process
UMC 28nm Logic and Mixed-Mode HLP/HVT process 12-Track POWERSLASH Cell Library (C35).
Standard Cell PowerSlash(TM) Library IP, RVT, 7 tracks, UMC 28nm HLP process
UMC 28nm HLP/RVT Logic and Mixed-Mode process 7-Track POWERSLASH Cell Library.
Standard Cell PowerSlash(TM) Library IP, LVT, 7 tracks, UMC 28nm HLP process
UMC 28nm HLP/LVT Logic and Mixed-Mode process 7-Track POWERSLASH Cell Library.
Standard Cell PowerSlash(TM) Library IP, HVT, 7 tracks, UMC 28nm HLP process
UMC 28nm HLP/HVT Logic and Mixed-Mode process 7-Track POWERSLASH Cell Library.
Standard Cell PowerSlash(TM) Library IP, RVT, 9 tracks, UMC 28nm HLP process
UMC 28nm Logic and Mixed-Mode HLP/RVT process 9-Track POWERSLASH Cell Library (C35).