IPSEC (RFC 4303) 1Gbit IP Core
The IPSEC core is a high performance pipelined implementation of the Encapsulating Security Protocol mode of IPSEC (RFC4303) with…
- IPsec / TLS
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
IPSEC (RFC 4303) 1Gbit IP Core
The IPSEC core is a high performance pipelined implementation of the Encapsulating Security Protocol mode of IPSEC (RFC4303) with…
PCI Express Differential Buffer IP, Single - Ended, UMC 90nm SP process
100MHz Reference Clock Single-end to Differential Buffer for PCIE Gen.II, UMC 55nm SP/RVT Low-K Logic process.
Metal Programmable IO IP, 1.8V/2.5V/3.3V Operations, UMC 0.18um G2 process
UMC 0.18um GII Logic process True 1.8V Metal-programmable IO (MPIO) Cell Library.
10/100 Ethernet PHY IP, UMC 90nm SP process
10/100 Base-TX Fast Ethernet PHY, UMC 90nm SP/RVT Low-K Logic process.
Standard Cell PowerSlash(TM) Library IP, HVT, UMC 90nm SP process
UMC 90nm SP/HVT Low-K process POWERSLASH Core Cell Library libary.
Standard Cell PowerSlash(TM) Library IP, RVT, UMC 90nm SP process
UMC 90nm SP/RVT Low-K process Low Power standard Cell Library.
Standard Cell PowerSlash(TM) Library IP, RVT, UMC 90nm LL process
UMC 90nm LL/RVT Low-K process Low Power POWERSLASH Core Cell Library.
Standard Cell PowerSlash(TM) Library IP, HVT, UMC 90nm LL process
UMC 90nm LL/HVT Low-K Logic process Cell Library POWERSLASH Core Cell Library (high density Version).
Standard Cell PowerSlash(TM) Library IP, HVT, UMC 65nm SP process
UMC 65nm SP/HVT process POWERSLASH Cell Library.
Standard Cell PowerSlash(TM) Library IP, RVT, UMC 65nm SP process
UMC 65nm SP/RVT Low-K Logic process Powerlash Core Cell Library.
Standard Cell PowerSlash(TM) Library IP, HVT, UMC 65nm LL process
UMC 65nm LL/HVT Low-K Logic process POWERSLASH Core Cell Library.
Standard Cell PowerSlash(TM) Library IP, RVT, UMC 65nm LL process
UMC 65nm LL/RVT Low-K process Mini-Library POWERSLASHKit.
Standard Cell PowerSlash(TM) Library IP, RVT, UMC 55nm SP process
UMC 55nm SP/RVT Low-K Logic process UHS Library POWERSLASH cells.
Standard Cell PowerSlash(TM) Library IP, RVT, 7 tracks, UMC 55nm SP process
UMC 55nm SP/RVT Logic process 7-Track POWERSLASH Cell Library.
Standard Cell PowerSlash(TM) Library IP, HVT, 7 tracks, UMC 55nm SP process
UMC 55nm SP/HVT Logic process 7-Track POWERSLASH Cell Library.
Standard Cell PowerSlash(TM) Library IP, HVT, 8 tracks, UMC 55nm SP process
UMC 55nm SP/HVT Low-K process POWERSLASH Cell Library.
Standard Cell PowerSlash(TM) Library IP, RVT, 12 tracks, UMC 55nm LP process
UMC 55nm LP/RVT Low-K Logic process 12-Track POWERSLASH Core Cell Library.
Standard Cell PowerSlash(TM) Library IP, LVT, 12 tracks, UMC 55nm LP process
UMC 55nm LP/LVT Low-K Logic process 12-Track POWERSLASH Core Cell Library.
Standard Cell PowerSlash(TM) Library IP, RVT, 7 tracks, UMC 55nm LP process
UMC 55nm LP/RVT Low-K Logic process 7-Track POWERSLASH Core Cell Library.
Standard Cell PowerSlash(TM) Library IP, LVT, 7 tracks, UMC 55nm LP process
UMC 55nm LP/LVT Low-K Logic process 7-Track POWERSLASH Core Cell Library.