Dual Port SRAM Compiler IP, High density, (2RW), UMC 0.13um HS/FSG process
UMC 0.13um HS/FSG Logic process high density synchronous Dual Port (2RW) SRAM memory compiler.
- UMC
- 130nm
- HS
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Dual Port SRAM Compiler IP, High density, (2RW), UMC 0.13um HS/FSG process
UMC 0.13um HS/FSG Logic process high density synchronous Dual Port (2RW) SRAM memory compiler.
DLL (All Digital) IP, Input: 5MHz - 70MHz, Output: 5MHz - 70MHz, UMC 40nm LP process
An ADDLL operate at 5MHz~70MHz.Output produce a rising/falling edge delay tuning clock.UMC 40nm LP/RVT Logic process.
DLL (All Digital) IP, Input: 360MHz - 720MHz, Output: 360MHz - 720MHz, UMC 40nm LP process
Input 360M-720MHz, output 360M-720MHz, DLL, Output 0-180 degree Phase adjustment range.
DLL (All Digital) IP, Input: 300MHz - 600MHz, Input: 300MHz - 600MHz, UMC 40nm LP process
An ADDLL operate at 300MHz~600MHz.Output 0-180 degree Phase adjustment range.Delay adjustment resolution
DDR DLL IP, Input: 66MHz - 200MHz, Output: 66MHz - 200MHz, UMC 90nm SP process
Input 66M-200MHz, output 66M-200MHz, DDR DLL, UMC 90nm SP/RVT Low-K Logic process.
DDR DLL IP, Input: 100MHz - 200MHz, Output: 100MHz -200MHz, UMC 0.18um G2 process
Input 100M-200MHz, output 100M-200MHz, DDR DLL, UMC 0.18um GII Logic process.
DDR DLL IP, Input: 100MHz - 200MHz, Output: 100MHz - 200MHz, UMC 0.13um HS/FSG process
Input 100M-200MHz, output 100M-200MHz, DDR DLL, UMC 0.13um HS/FSG Logic process.
DDR DLL IP, Input: 100MHz - 150MHz, Output: 100MHz - 150MHz, UMC 0.18um G2 process
Input 100M-150MHz, output 100M-150MHz, DDR DLL, UMC 0.18um GII Logic process.
PWM controller with soft start function for DC to DC boost converter, UMC 0.13um HS/FSG Logic process.
DC-DC IP, Input: 3.3V, Output: 5V/50mA, UMC 0.18um G2 process
Pulse width modulation, boosting voltage from 3.3V to 5V, 50mA driving capability, Ivcca=140uA @ Idrive=0.
D/A Converter IP, UMC 40nm LP process
10-Bit 150MSPS 1-ch Video Digital-to-Analog converter, UMC 40nm LP/RVT Low-K proces.
D/A Converter IP, 16/18/20/24 bits, 192Ksps, UMC 0.13um SP process
16/18/20/24-Bit input format supporting 192KSPS output stereo-line Digital-to-Analog converter with headphone driver, UMC 0.13um …
D/A Converter IP, 10 bits, 250Msps, UMC 90nm SP process
10-Bit 250MHz 3-channel Digital-to-Analog converter, UMC 90nm SP/RVT Low-K process.
D/A Converter IP, 10 bits / 1MHz, Voltage output, UMC 0.13um HS/FSG process
10-Bit 1MHz R-2R Digital-to-Analog converter, UMC Logic 0.13um HS/FSG process.
D/A Converter IP, 10 bits, 150Msps, UMC 40nm LP process
10-Bit 150MSPS 3-ch Video Digital-to-Analog converter, UMC 40nm LP/RVT Low-K process.
D/A Converter IP, 10 bits, 150Msps, differential current Output, UMC 90nm SP process
10-Bit 150MSPS current output differential-end Digital-to-Analog converter, UMC 90nm SP/RVT Logic Low-K process.
10-Bit Digital-to-Analog converter for communication system, UMC 0.18um GII Logic process.
10-Bit 250MSPS 3 channel current output single-end Digital-to-Analog converter, UMC 0.13um HS/FSG Logic process.
D/A Converter IP, 10 bits / 150Msps, Current Output: / Single end, UMC 0.18um G2 process
10-Bit 150MSPS current output single-end Digital-to-Analog converter, UMC 0.18um GII Logic process.
D/A Converter IP, 10 bits / 150Msps, Current Output: / Differential end, UMC 0.13um LL/FSG process
10-Bit 150MSPS current output differential-end Digital-to-Analog converter, UMC 0.13um LL Logic/FSG process.