Standard Cell (MiniLib) Library IP, 7 tracks, UMC 0.13um HS/FSG process
UMC 0.13um HS/FSG Logic process high density Core Cell Library.
- UMC
- 130nm
- HS
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Standard Cell (MiniLib) Library IP, 7 tracks, UMC 0.13um HS/FSG process
UMC 0.13um HS/FSG Logic process high density Core Cell Library.
Standard Cell (Generic) Library IP, 10-track, RVT, UMC 90nm SP process
UMC 90nm SP Logic Low-K process standard Core Cell Library.
Standard Cell (Generic) Library IP, UMC 0.25um process
UMC 0.25um Logic process standard Cell Library.
Standard Cell (Generic) Library IP, UMC 0.25um process
UMC 0.25um Logic process standard Cell Library.
Standard Cell (Generic) Library IP, UMC 0.25um process
UMC 0.25um Logic process mask programmable cell array with body E Core Cell Library.
Standard Cell (Generic) Library IP, UMC 0.25um process
UMC 0.25um Logic process shrink (0.22um) mask programmable cell array with body A Core Cell Library.
Standard Cell (Generic) Library IP, UMC 0.18um MS process
UMC 0.18um Mixed-Mode / RFCMOS process standard Core Cell Library.
Standard Cell (Generic) Library IP, UMC 0.18um LL process
UMC 0.18um LL Logic process mask programmable cell array with body E Core Cell Library.
Standard Cell (Generic) Library IP, UMC 0.18um LL process
UMC 0.18um LL Logic process standard Core Cell Library.
Standard Cell (Generic) Library IP, UMC 0.18um G2 process
UMC 0.18um GII Logic process standard Core Cell Library.
Standard Cell (Generic) Library IP, UMC 0.18um G2 process
UMC 0.18um GII Logic process mask programmable cell array with body E Core Cell Library.
Standard Cell (Generic) Library IP, UMC 0.15um SP process
UMC 0.15um SP Logic process mask programmable cell array with body E Core Cell Library.
Standard Cell (Generic) Library IP, UMC 0.13um SP process
UMC 0.13um Logic high speed(FSG) process, Metal programmable(M3/M4/M5) cell array Core Cell Library.
Standard Cell (Generic) Library IP, UMC 0.13um SP process
UMC 0.13um SP/FSG Logic process mask programmable cell array with body E Core Cell Library.
Standard Cell (Generic) Library IP, UMC 0.13um LL/FSG process
UMC 0.13um LL Logic(FSG) process metal programmable (M3/M4/M5) cell array standard Core Cell Library.
Standard Cell (Generic) Library IP, UMC 0.13um LL process
UMC 0.13um LL Logic/FSG process mask programmable cell array with body E Core Cell Library.
Standard Cell (Generic) Library IP, UMC 0.13um LL process
UMC 0.13um LL process, standard Cell Library.
Standard Cell (Generic) Library IP, UMC 0.13um LL process
UMC 0.13um LL FSG process high density Generic Core Cell Library.
Standard Cell (Generic) Library IP, UMC 0.13um LL process
UMC 0.13um LL Logic/FSG process high density Core Cell Library.
Standard Cell (Generic) Library IP, UMC 0.13um HS/FSG process
UMC 0.13um HS/FSG Logic process metal programmable (M3/M4/M5) cell array standard Core Cell Library.