Two Port Register File Compiler IP, UMC 0.13um HS/FSG process
UMC 0.13um HS/FSG Logic process Synchronous Two Port Register File SRAM memory compiler.
- UMC
- 130nm
- HS
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Two Port Register File Compiler IP, UMC 0.13um HS/FSG process
UMC 0.13um HS/FSG Logic process Synchronous Two Port Register File SRAM memory compiler.
Two Port Register File Compiler IP, UMC 0.13um HS/FSG process
UMC 0.13um HS/LL fusion (FSG) process high density synchronous Two Port Register File SRAM memory compiler.
Two Port Register File Compiler IP, UMC 0.11um LL/FSG process
UMC 0.11um Logic(LL) FSG process synchronous Two Port Register File memory compiler.
Two Port Register File Compiler IP, UMC 0.11um HS/FSG process
UMC 0.11um HS Logic process synchronous Two Port Register File SRAM memory compiler.
Two Port Register File Compiler IP, UMC 0.11um HS/AE process
UMC 0.11um HS/AE (AL Enhancement) Logic process synchronous Two Port Register File memory compiler.
Two Port Register File Compiler IP, UMC 0.11um eFlash/HS process
UMC 0.11um eFlash HS process, Two Port Register File.
Standard Cell PowerSlash(TM) Library IP, RVT, UMC 55nm SP process
UMC 55nm SP/RVT Low-K Logic process Powerlash Core Cell Library.
Standard Cell PowerSlash(TM) Library IP, RVT, 7 tracks, UMC 28nm HPC process
UMC 28nm HPC/RVT Logic and Mixed-Mode process 7-Track POWERSLASH Cell Library (C35).
Standard Cell PowerSlash(TM) Library IP, RVT, 7 tracks, UMC 28nm HLP process
UMC 28nm HLP/RVT Logic and Mixed-Mode process 7-Track POWERSLASH Cell Library with LPLUS (C38).
Standard Cell PowerSlash(TM) Library IP, RVT, 7 tracks, UMC 28nm HLP process
UMC 28nm HLP/RVT Logic and Mixed-Mode process 7-Track POWERSLASH Cell Library with LMINUS (C30 RVT).
Standard Cell PowerSlash(TM) Library IP, LVT, 9 tracks, UMC 28nm HLP process
UMC 28nm HLP/LVT Logic process 9-Track POWERSLASH standard Core Cell Library (C35).
Standard Cell PowerSlash(TM) Library IP, LVT, 7 tracks, UMC 28nm HPC process
UMC 28nm HPC/LVT Logic and Mixed-Mode process 7-Track POWERSLASH Cell Library (C35).
Standard Cell PowerSlash(TM) Library IP, LVT, 7 tracks, UMC 28nm HLP process
UMC 28nm HLP/LVT Logic and Mixed-Mode process 7-Track POWERSLASH Generic Core Cell Library wtih LPLUS (C38).
Standard Cell PowerSlash(TM) Library IP, LVT, 7 tracks, UMC 28nm HLP process
UMC 28nm HLP/LVT Logic and Mixed-Mode process 7-Track POWERSLASH Cell Library with LMINUS (C30).
Standard Cell PowerSlash(TM) Library IP, HVT, 9 tracks, UMC 28nm HLP process
UMC 28nm HLP/HVT Logic process 9-Track POWERSLASH Core Core Cell Library.
Standard Cell PowerSlash(TM) Library IP, HVT, 7 tracks, UMC 28nm HPC process
UMC 28nm HPC/HVT Logic and Mixed-Mode process 7-Track POWERSLASH Kit Cell Library C35.
Standard Cell PowerSlash(TM) Library IP, HVT, 7 tracks, UMC 28nm HLP process
UMC 28nm HLP/HVT Logic and Mixed-Mode process 7-Track Generic Core Cell Library with LPLUS (C38).
Standard Cell (Ultra High Speed) Library IP, RVT, 12 tracks, UMC 40nm LP process
UMC 40nm LP/RVT Low-K Logic process 12-Track high performance Cell Library.
Standard Cell (Ultra High Speed) Library IP, LVT, 12 tracks, UMC 40nm LP process
UMC 40nm LP/LVT Low-K Logic process 12-Track high performance Cell Library.
Standard Cell (Ultra High Speed) Library IP, HVT, 12 tracks, UMC 40nm LP process
UMC 40nm LP/HVT Low-K Logic process 12-Track Standard Cell Library.