UMC 40nm LP/RVT Logic Process 1.8V/3.0V multi-voltage BOAC eMMC I/O cell library
UMC 40nm LP/RVT Logic Process 1.8V/3.0V multi-voltage BOAC eMMC I/O cell library
- UMC
- 40nm
- LP
- Pre-Silicon
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
UMC 40nm LP/RVT Logic Process 1.8V/3.0V multi-voltage BOAC eMMC I/O cell library
UMC 40nm LP/RVT Logic Process 1.8V/3.0V multi-voltage BOAC eMMC I/O cell library
UMC 65nm LL/RVT 1P10M LowK Logic Process 1.8V/3.3V multi-voltage generic I/O cell library
UMC 65nm LL/RVT 1P10M LowK Logic Process 1.8V/3.3V multi-voltage generic I/O cell library
UMC 0.13um HS/FSG Logic Process Ultra-slim SSTL-2 (ClassI)/LVTTL (10mA) Combo I/O Cells
UMC 0.13um HS/FSG Logic Process Ultra-slim SSTL-2 (ClassI)/LVTTL (10mA) Combo I/O Cells
UMC 0.11um HS/AL Logic Process True 3.3V Standard IO Cell Library
UMC 0.11um HS/AL Logic Process True 3.3V Standard IO Cell Library
UMC 55nm SP/RVT LowK Logic Process True 3.3V Generic IO Cell Library
UMC 55nm SP/RVT LowK Logic Process True 3.3V Generic IO Cell Library
UMC 0.18um Logic GII Process true 3.3V RTC IO cell Library
UMC 0.18um Logic GII Process true 3.3V RTC IO cell Library
UMC 28nm Logic and Mixed-Mode HPC Process 3.3V Analog ESD IO cell Library
UMC 28nm Logic and Mixed-Mode HPC Process 3.3V Analog ESD IO cell Library
UMC 28nm Logic and Mixed-Mode HPC Process, 1.8V Analog ESD IO cell Library
UMC 28nm Logic and Mixed-Mode HPC Process, 1.8V Analog ESD IO cell Library
UMC 28nm Logic and Mixed-Mode HPC Process,0.9V Analog ESD IO cell Library
UMC 28nm Logic and Mixed-Mode HPC Process,0.9V Analog ESD IO cell Library
Analog part of 600Mbps to 4Gbps 8-lane V-By-One transmitter with embedded PLL circuit, VCC=0.9V; UMC 28nm HPC+ LowK Logic Process.
28nm HPC+ USB3.1 gen2 PHY(10Gbps)
28nm HPC+ USB3.1 gen2 PHY(10Gbps)
28nm HPC USB3.1 gen2 PHY(10Gbps)
28nm HPC USB3.1 gen2 PHY(10Gbps)
USB 3.0 PHY; UMC 28nm HPC_Plus +RVT+LVT Logic Process
USB 3.0 PHY; UMC 28nm HPC_Plus +RVT+LVT Logic Process
USB 2.0 On-The-Go PHY; UMC 40nm Logic LP/RVT Low-K Process
USB 2.0 On-The-Go PHY; UMC 40nm Logic LP/RVT Low-K Process
USB 2.0 On-The-Go PHY; UMC 28nm HPC+ RVT Logic Process
USB 2.0 On-The-Go PHY; UMC 28nm HPC+ RVT Logic Process
USB2.0 OTG PHY UMC 40nm LP/RVT process, for Flip chip Bump type_LF
USB2.0 OTG PHY UMC 40nm LP/RVT process, for Flip chip Bump type_LF
USB 2.0 On-The-Go PHY, analog part ; UMC 28nm HPC RVT Logic Process
USB 2.0 On-The-Go PHY, analog part ; UMC 28nm HPC RVT Logic Process
28Gb/s 4 lane high-speed SerDes; UMC 28nm HPC Logic Std/HS process
28Gb/s 4 lane high-speed SerDes; UMC 28nm HPC Logic Std/HS process
UMC 28nm HPC+, 4-Lane 1.25~12.5 Gbps SERDES
UMC 28nm HPC+, 4-Lane 1.25~12.5 Gbps SERDES
PCIE Gen.II PHY; UMC 65nm LP/RVT LowK Logic Process.
PCIE Gen.II PHY; UMC 65nm LP/RVT LowK Logic Process.