Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process
- Controller + PHY + 1
- UMC
- 55nm
- LP
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Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process
Input 400M-1600MHz, output 400M-1600MHz, all digital slave delay line of FXADDLL340HH0L to generate 25% delay in period of FREF, …
12 bit 1MSPS R-2R DAC; UMC 55nm eFlash process
12 bit 1MSPS R-2R DAC; UMC 55nm eFlash process
12bits 1MHz Voltage output R-2R D/A Converter; UMC 55nm SP-RVT process
12bits 1MHz Voltage output R-2R D/A Converter; UMC 55nm SP-RVT process
10bits 1MHz R-2R D/A Converter with rail to rail voltage output ; UMC 55nm ULP process
10bits 1MHz R-2R D/A Converter with rail to rail voltage output ; UMC 55nm ULP process
10bits 1MHz R-2R D/A Converter with rail to rail voltage output ; UMC 55nm eFlash (SST) process
10bits 1MHz R-2R D/A Converter with rail to rail voltage output ; UMC 55nm eFlash (SST) process
10bit 250MSPS Current-steering Video D/A Converter; UMC 0.11um HS/FSG Logic Process
10bit 250MSPS Current-steering Video D/A Converter; UMC 0.11um HS/FSG Logic Process
10bit 150MSPS 3-ch Video DAC,UMC 28nm HPC process
10bit 150MSPS 3-ch Video DAC,UMC 28nm HPC process
CMM lane operating from 1.25G~8G ,UMC 28nm HPC Process
CMM lane operating from 1.25G~8G ,UMC 28nm HPC Process
MIPI Transmitter CPHY 80Msps~2.5Gsps; DPHY 80Mbps~2.5Gbps ; UMC 28nm HPC process
MIPI Transmitter CPHY 80Msps~2.5Gsps; DPHY 80Mbps~2.5Gbps ; UMC 28nm HPC process
MIPI Receiver CPHY 80Msps~2.5Gsps; DPHY 80Mbps~2.5Gbps ; UMC 28nm HPC process_x005F_x000D_
MIPI Receiver CPHY 80Msps~2.5Gsps; DPHY 80Mbps~2.5Gbps ; UMC 28nm HPC process
Power input 1.8v, VBG=0.75V Band-gap, UMC 28nm HPC Logic process
Power input 1.8v, VBG=0.75V Band-gap, UMC 28nm HPC Logic process
Input 1.62V-1.98V, VBG=0.3V BandGap ; UMC 28nm process HPC+ Process
Input 1.62V-1.98V, VBG=0.3V BandGap ; UMC 28nm process HPC+ Process
Input 1.62V-1.98V, VBG=0.3V BandGap ; UMC 28nm process HPC Process
Input 1.62V-1.98V, VBG=0.3V BandGap ; UMC 28nm process HPC Process
Input 1.2V, VBG=0.8V BandGap; UMC 65nm LL/RVT LowK Logic Process_x005F_x000D_ _x005F_x000D_
Input 1.2V, VBG=0.8V BandGap; UMC 65nm LL/RVT LowK Logic Process
Input 2.0V-3.6V, VBG=1.2V Band-gap, UMC 55nm LP/RVT Logic Process
Input 2.0V-3.6V, VBG=1.2V Band-gap, UMC 55nm LP/RVT Logic Process
Input 2.0V-3.6V, VBG=1.2V Band-gap, UMC 55nm eflash LP/RVT Logic Process
Input 2.0V-3.6V, VBG=1.2V Band-gap, UMC 55nm eflash LP/RVT Logic Process
Input 2.5V, VBG=1.23V BandGap; UMC 40nm LP/RVT LowK Logic Process_x005F_x000D_
Input 2.5V, VBG=1.23V BandGap; UMC 40nm LP/RVT LowK Logic Process
Power input 3.3V, VBG=1.204V Band-gap, UMC 55nm eFlash process
Power input 3.3V, VBG=1.204V Band-gap, UMC 55nm eFlash process
FXAFE030HH0L is an Analog Front End IP for image processing applications.