Input 20M-66M Hz, output 400M-800M Hz, frequency synthesizable PLL; UMC 55nm EFLASH/EE2PROM ULP RVT LowK Logic Process
- UMC
- 55nm
- ULP
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Input 20M-66M Hz, output 400M-800M Hz, frequency synthesizable PLL; UMC 55nm EFLASH/EE2PROM ULP RVT LowK Logic Process
1~50V/V low offset PGA for SAR-ADC ; UMC 0.18um Mixed-Mode PROCESS
1~50V/V low offset PGA for SAR-ADC ; UMC 0.18um Mixed-Mode PROCESS
An 8-bit 10MSPS Programmable Gain Amplifier ;UMC 55nm SP-HVT LowK Logic Process
An 8-bit 10MSPS Programmable Gain Amplifier ;UMC 55nm SP-HVT LowK Logic Process
NO External-R ,frequency 30K~60K ,RC Oscillator .
Internal-R, frequency 48MHz/8MHz. Input 1.08V-1.32V; UMC 55nm EFLASH process
Internal-R, frequency 48MHz/8MHz.
Self-contained ring oscillator, frequency 32KHz.
55nm-SP, FPD-Link Receiver, 3.3V/1.0V, 4 data plus 1 clock channel, 16~85MHz, DLL type,
55nm-SP, FPD-Link Receiver, 3.3V/1.0V, 4 data plus 1 clock channel, 16~85MHz, DLL type,
1.8v LVDS RX IO 800Mbps, UMC 40nm LP/RVT LowK Logic Process
1.8v LVDS RX IO 800Mbps, UMC 40nm LP/RVT LowK Logic Process
MIPI Transmitter 80~1500MHz combo with CMOS input using MIFS C40LP Logic Process
MIPI Transmitter 80~1500MHz combo with CMOS input using MIFS C40LP Logic Process
MIPI RX 80Mbps~2.5Gbps ; UMC 28nm HPC+ process
MIPI RX 80Mbps~2.5Gbps ; UMC 28nm HPC+ process
Input 80MHz-440MHz, DQS delay 1/32 and 1/16 of FREF period, UMC 40nm LP/RVT Low-K logic process.
Input 80MHz-440MHz, DQS delay 1/32 and 1/16 of FREF period, UMC 40nm LP/RVT Low-K logic process.
Data Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for copper pillar bump Flip chip version ; UMC 40nm LP LowK Logic Process
Command/Address Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY supporting 2-rank application for Copper Pillar Bump Flip Chip Version…
DDR3 RTL Digitalize PHY DATA block; UMC 28nm HPC/RVT Logic Process using FSJ0C_ARS
DDR3 RTL Digitalize PHY DATA block; UMC 28nm HPC/RVT Logic Process using FSJ0C_ARS
DDR3 RTL Digitalize PHY AC block; UMC 28nm HPC/RVT Logic Process using FSJ0C_ARS
DDR3 RTL Digitalize PHY AC block; UMC 28nm HPC/RVT Logic Process using FSJ0C_ARS
Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process
Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process
Compensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for SIP Application; UMC 28nm HPC/RVT LowK Logic Process; Vertical v…
Compensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY; UMC 55nm LP/RVT LowK Logic Process
Compensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY; UMC 55nm LP/RVT LowK Logic Process
Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process