The DDR5/4 PHY is a physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring hi…
- Controller + PHY + 1
- DDR5
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
The DDR5/4 PHY is a physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring hi…
DDR Secure Controller supporting DDR5
The DDR5/4 Controller is a next-generation memory controller optimized for latency, bandwidth, and area, supporting JEDEC standar…
DDR Low Latency Controller supporting DDR5
The DDR5/4 Controller is a next-generation memory controller optimized for latency, bandwidth, and area, supporting JEDEC standar…
DDR Controller supporting DDR5 with Advanced Features Package
The DDR5/4 Controller is a next-generation memory controller optimized for latency, bandwidth, and area, supporting JEDEC standar…
DDR Controller supporting DDR5 with a CHI interface and Advanced Feature Package
The DDR5/4 Controller is a next-generation memory controller optimized for latency, bandwidth, and area, supporting JEDEC standar…
DDR Controller supporting DDR5 MRDIMM Gen2 with Advanced Features Package
The DDR5/4 Controller is a next-generation memory controller optimized for latency, bandwidth, and area, supporting JEDEC standar…
DDR Controller supporting DDR5 and DDR4 with Advanced Features Package
The DDR5/4 Controller is a next-generation memory controller optimized for latency, bandwidth, and area, supporting JEDEC standar…
DDR Controller supporting DDR5 and DDR4 with a CHI interface and Advanced Feature Package
The DDR5/4 Controller is a next-generation memory controller optimized for latency, bandwidth, and area, supporting JEDEC standar…
DDR Controller supporting DDR5 and DDR4 with a CHI interface
The DDR5/4 Controller is a next-generation memory controller optimized for latency, bandwidth, and area, supporting JEDEC standar…
DDR Controller supporting DDR5 and DDR4
The DDR5/4 Controller is a next-generation memory controller optimized for latency, bandwidth, and area, supporting JEDEC standar…
PCIe 6.0 PHY, SS SF5A x4, North/South (vertical) poly orientation
The multi-channel PHY IP for PCI Express® (PCIe®) 6.x meets today’s demands for higher bandwidth and power efficiency across netw…
PCIe 6.0 PHY, SS SF5A x1, North/South (vertical) poly orientation
The multi-channel PHY IP for PCI Express® (PCIe®) 6.x meets today’s demands for higher bandwidth and power efficiency across netw…
PCIe 6.0 PHY, SS SF4X x4, North/South (vertical) poly orientation
The multi-channel PHY IP for PCI Express® (PCIe®) 6.x meets today’s demands for higher bandwidth and power efficiency across netw…
PCIe 6.0 PHY, SS SF2 x4, North/South (vertical) poly orientation
The multi-channel PHY IP for PCI Express® (PCIe®) 6.x meets today’s demands for higher bandwidth and power efficiency across netw…
PCIe 6.0 PHY G2 , TSMC N5 x4, North/South (vertical) poly orientation
The multi-channel PHY IP for PCI Express® (PCIe®) 6.x meets today’s demands for higher bandwidth and power efficiency across netw…
PCIe 6.0 PHY G2 , TSMC N5 x2, North/South (vertical) poly orientation
The multi-channel PHY IP for PCI Express® (PCIe®) 6.x meets today’s demands for higher bandwidth and power efficiency across netw…
PCIe 5.0 PHY, TSMC N5 x4, North/South (vertical) poly orientation
The multi-channel PHY IP for PCI Express® (PCIe®)5.0 and CXL includes a high-speed, high-performance transceiver to meet today’s …
PCIe 5.0 PHY, TSMC N5 x2, North/South (vertical) poly orientation
The multi-channel PHY IP for PCI Express® (PCIe®)5.0 and CXL includes a high-speed, high-performance transceiver to meet today’s …
PCIe 5.0 PHY, TSMC N5 x16, North/South (vertical) poly orientation
The multi-channel PHY IP for PCI Express® (PCIe®)5.0 and CXL includes a high-speed, high-performance transceiver to meet today’s …
PCIe 5.0 PHY, NCS,TSMC N5 x4, North/South (vertical) poly orientation
The multi-channel PHY IP for PCI Express® (PCIe®)5.0 and CXL includes a high-speed, high-performance transceiver to meet today’s …