DDR3 and DDR4 Controller and PHY on TSMC 12nm
This DDR3/4 IP combo solution presented, is meticulously designed for high performance and low power consumption, utilizing sophi…
- Controller + 1
- TSMC
- 12nm
- FFC
- Available on request
DDR3 and DDR4 Controller and PHY on TSMC 12nm
This DDR3/4 IP combo solution presented, is meticulously designed for high performance and low power consumption, utilizing sophi…
As the demand for higher data rates and increased serial I/O density intensifies, the performance requirements for next-generatio…
KA13UGUSB20ST001 is USB2.0 physical layer transceiver (PHY) integrated circuits.
LVDS IO handling data rate up to 50Mbps with maximum loading 60pF
KA16UGLVDS01ST001 is a LVDS IO handling data rate up to 50Mbps with a maximum loading of 60pF.
USB 2.0 On-chip oscillator, termination resistors, and DP/DM short circuit protection (0.18u)
The KA18USB20 consists of the digital and analog blocks of the USB Transceiver Macrocell (UTMI) specifications.
The KA13ETHB33 is a single-port PHY with an MII (Media Independent Interface).
The inline CUP I/O library provide 3.3V bi- directional I/O cells with pull -up, pull-down features, Schmitt trigger and a range …
PHY layer solution for PCIe1.1/PCIe2.0 with a serial interface and PIPE3 compliant digital interface
KA13UGPEP20ST001 provides a PHY layer solution for PCIe1.1/PCIe2.0 (2.5/5.0Gbps) for single lane application.