Our analog-to-digital converter is a configurationally general-purpose ADC that uses a traditional Charge-Redistribution SAR arch…
- ADC
Our analog-to-digital converter is a configurationally general-purpose ADC that uses a traditional Charge-Redistribution SAR arch…
The Serial ATA Host IP Core provides an interface to high-speed serial link replacements for the parallel ATA attachment of mass …
32KHz XTAL oscillator specifically designed for ultra low power applications.
Our MIPI-D-PHY IP is a high-frequency low-power, low-cost, source-synchronous, Physical Layer that supports the MIPI Alliance Sta…
Our Processor for high embedded performance with RISC-V instruction-set compatibility, permit users to grasp the rich ecosystem o…
The demand for multimedia features are pushing device manufacturers to integrate more peripherals such as multi-megapixel cameras…
The NFC transceiver is considered for adding NFC functionality to mobile devices and other applications having embedded MCU.
The Multi-protocol SerDes (MPS) PHY is a comprehensive PAM-4 solution that provides high-performance, multi-lane capability and l…
The Controller Area Network – Flexible Data (CAN-FD) controller IP implements the CAN 2.0A, CAN 2.0B as well as newer high-perfor…
The Ethernet Media Access Controller IP is an embedded Fast Ethernet controller module.
Precision Time Protocol or PTP or IEEE1588 is one such protocol that allows synchronization of an order of 1us with the master (m…
External Flash Memory Interface IP
Flash memory forms a basic constituent in many FPGA based embedded systems using Xilinx SRAM based FPGAs.
HDMI transmitter PHY (Physical layer) IP core which is fully amenable with HDMI 1.4/2.0 specification.HDMI transmitter PHY which …
We offer high-performance silicon-proven as measured by resource use, gate count, and latency.
We propound best in class fully customizable PCIe 3.0 PHY, targeted for both enterprise and client application, the complaint to …
SD/SDIO Combo Device IP core is an SD memory controller and an SDIO controller with an AHB interface.
I3C Master and Slave Dual Controller IP
This is an I3C Master and Slave Dual Controller IP which can manage Master as well as Slave and encounters the MIPI I3C standard.
Our Video Encoder IP Core is a real-time, true multi-format hardware encoder IP supporting H.264/AVC, H.265/HEVC, VP9 video codec…
LPDDR4/3 provides very intense presentation via memory controller design based on proprietary out-of-order scheduling algorithm a…
The programmable Fractional-N PLL to lock to an incoming clock source and produce an output clock with a non-integer multiplicati…