UCIe 3.0 IP
ForwardEdge’s UCIe IP enables scalable die-to-die connectivity for chiplet-based SoCs.
Overview
ForwardEdge’s UCIe IP enables scalable die-to-die connectivity for chiplet-based SoCs. Supporting x16 link width with speeds up to 16 GT/s per lane, it conforms to UCIe’s standardized interface for seamless chiplet integration. Developed on GlobalFoundries 12LP+, this IP includes custom PHY, protocol, and die-to-die layers—engineered for performance, flexibility, and low latency.
Block Diagram
Benefits
- Silicon Proven: Proven on GlobalFoundries 12LP+ node.
- 100% Domestic Supply Chain: Developed, fabricated, assembled, and tested entirely with U.S. onshore resources.
- High Performance: High-bandwidth, ultra-low-latency die-to-die connectivity with optimized power efficiency.
- De-Risked Integration: Standards-based interoperability reducing development risk across heterogeneous package architectures.
- Target Applications: Optimized for AI accelerators, data center infrastructure, networking, storage, aerospace, defense, and edge computing.
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| GlobalFoundries | 12nm | LP+ | Silicon Proven |
Specifications
Identity
Files
Note: some files may require an NDA depending on provider policy.
Provider
Learn more about UCIe IP core
Frequently asked questions about UCIe IP cores
What is UCIe 3.0 IP?
UCIe 3.0 IP is a UCIe IP core from ForwardEdge ASIC listed on Semi IP Hub. It is listed with support for globalfoundries Silicon Proven.
How should engineers evaluate this UCIe?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this UCIe IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.