UA Link DL IP core

Silicon agnostic and fully compliant implementation of UALink_200 specification

The UA Link DL IP Core is a high-performance, silicon-agnostic and fully compliant Data Layer implementation of UALink_200 specifi cation. Designed for seamless integration into accelerator, switch, and SoC designs, it delivers deterministic low-latency, robust error correction, and compatibility with multiple high-speed Ethernet-derived link rates.

This IP core bridges the UALink Transaction Layer (TL) to the UA Link Ethernet Physical Coding Sublayer (PCS), ensuring optimized fl it packing and unpacking, coordinating changes to the link, and providing a UART mechanism for fi rmware-controlled sequence passing as defi ned in UALink_200 Standard. It is ideal for systems requiring 200–800 Gbps per Link/Station with industry leading signal integrity and interoperability.

• UALink_200 Specifi cation Compliant: Implements DL functions per Rev 1.0
• Multi-Rate Support : 200 GBASE-KR1/CR1, 400 GBASE-KR2/CR2, 800 GBASE-KR4/CR4
• Tx Pacing/Rx rate adaptation
• Provides a Data Link Layer message service between link partners
• Link Level Replay on 640 Byte fl it basis
• 32 bit CRC for error checking
• Targeting both ASICs and FPGAs

The IP Core can be delivered in Source code or Encrypted format.

The following deliverables will be provided with the IP Core license:

• Solid documentation, including User Manual, Release Note and Quick Start Guide.
• Simulation Environment, including Simple Testbed, Test case, Test Script.
• Timing Constraints in Synopsys SDC format.
• Access to support system and direct support from Chip Interfaces Engineers.
• Test Report , Synopsys SGDC Files and Synopsys Lint, CDC and Waivers available on request