Silicon agnostic and fully compliant Physical Coding Sublayer (PCS) implementation of UALink_200 specification The UA Link PCS IP…
- UALink
UALink IP cores enable high-bandwidth die-to-die connectivity in advanced packaging and chiplet architectures in modern SoC and ASIC designs.
These IP cores support accelerator-oriented scale-up and die-to-die connectivity in next-generation AI and data-center fabrics, helping designers scale heterogeneous integration with better bandwidth density, packaging flexibility, and subsystem reuse
This catalog allows you to compare UALink IP cores from leading vendors based on bandwidth, latency, power efficiency, and process node compatibility.
Whether you are designing AI scale-up systems, accelerator fabrics, data-center packages, or high-performance interconnect platforms, you can find the right UALink IP for your application.
Silicon agnostic and fully compliant Physical Coding Sublayer (PCS) implementation of UALink_200 specification The UA Link PCS IP…
Efficient scaling of AI accelerators is necessary for achieving breakthrough performance and throughput in modern compute environ…
The UALink IP solution, consisting of UALink Controller, PHY, and verification IP, is designed to meet the performance requiremen…
Silicon agnostic and fully compliant implementation of UALink_200 specification The Chip Interfaces UA Link TL IP Core is a high-…
Silicon agnostic and fully compliant implementation of UALink_200 specification The UA Link DL IP Core is a high-performance, sil…
The Ultra Accelerator Link (UALink) Verification IP (VIP) provides a bus functional model (BFM) with integrated automatic protoco…
224G SerDes PHY and controller for UALink for AI systems
Efficient Scaling of AI Accelerators for Achieving High Performance and Throughput UALink, the standard for AI accelerator interc…
Specifications: UAL_200 1.0 Interfaces: 802.3 dj compliant, UPLI DUT Types/Topology: Protocol TL Phy DL Reconciliation Sub Layer…