Vendor: Cadence Design Systems, Inc. Category: UALink

UALink Controller

Efficient scaling of AI accelerators is necessary for achieving breakthrough performance and throughput in modern compute environ…

Overview

Efficient scaling of AI accelerators is necessary for achieving breakthrough performance and throughput in modern compute environments. The UALink Controller, part of Cadence’s verified UALink IP subsystem, delivers ultra-low latency and high-bandwidth interconnects that enable seamless scale-up connectivity between AI accelerators. It supports memory semantics for read, write, and atomic operations, ensuring fast, coherent data handling across workloads. UALink IP provides a scalable, future-ready solution for next-generation AI infrastructure.

As a contributor member of the UALink Consortium, Cadence offers a complete UALink solution—including controller, PHY, drivers, and verification IP—optimized for both short- and long-reach applications.

Key features

  • Multi-Line Rate Support: Compatible with 100G and 200G data rates (per lane).
  • FEC Interleave Options: 1-way, 2-way, and 4-way interleave modes for latency optimization.
  • Integrated Debugging Tools: Includes flit-play for error injection and flit-capture for field diagnostics.
  • Security Enhancements: Optional secure layer integration for authentication and encryption.
  • Protocol Flexibility: Supports all 1.0 features.

Block Diagram

Benefits

  • Power-Efficient Design: Engineered for optimal performance-per-watt across AI workloads.
  • Low-Latency Architecture: Minimizes communication delays for real-time responsiveness.
  • Scalability: Optimized PHY, PCS, and controller for scale-up connectivity.
  • Proven Solution: Fully verified protocol stack with controller and PHY integration.

Files

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Specifications

Identity

Part Number
UALink Controller
Vendor
Cadence Design Systems, Inc.
Type
Silicon IP

Provider

Cadence Design Systems, Inc.
HQ: USA
If you want to achieve silicon success, let Cadence help you choose the right IP solution and capture its full value in your SoC design. Cadence® IP solutions offer the combined advantages of a high-quality portfolio, an open platform, a modern IP factory approach to quality, and a strong ecosystem. Now you can tackle IP-to-SoC development in a system context, focus your internal effort on differentiation, and leverage multi-function cores to do more, faster. The Cadence IP Portfolio includes silicon-proven Tensilica® IP cores, analog PHY interfaces, standards-based IP cores, verification IP cores, and other solutions as well as customization services for current and emerging industry standards. The Cadence IP Factory provides you with an automated approach to the customization, delivery, and verification of SoC IP. As a result, you can spend more time on differentiation, with the assurance that you'll meet your performance, power, and area requirements. Choosing Cadence IP enables you to design with confidence because you have more freedom to innovate your SoCs with less risk and faster time to market.

Learn more about UALink IP core

Validating UPLI Protocol Across Topologies with Cadence UALink VIP

The UPLI (UALink Protocol Level Interface) is a logical signaling interface that facilitates communication between devices—specifically between originator devices (which initiate transactions) and completer devices (which respond to them). Each transaction comprises a request and a corresponding response, forming a complete communication cycle. Cadence UALink VIP supports various topologies to verify UPLI layer of DUT.

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

At the recent ECOC 2025 conference in Copenhagen, Cadence showcased its key role in enabling the future of AI infrastructure with live silicon demonstrations of several essential IP technologies for emerging 800G and 1.6T networks. Powered by Cadence's 224G SerDes IP, Cadence's Ultra Accelerator Link (UALink 1.0) scale-up and Ultra Ethernet scale-out networking solutions deliver the performance, flexibility, and interoperability needed for next-generation AI factories and hyperscale data centers.

How Ultra Ethernet And UALink Enable High-Performance, Scalable AI Networks

This article delves into the technical aspects of how scaling up and out is becoming a critical need for HPC and AI chip developers, and how new standards such as Ultra Ethernet and Ultra Accelerator Link (UALink) aim to tackle the challenges of high-bandwidth, low-latency connectivity and efficient resource management.

Frequently asked questions about UALink IP cores

What is UALink Controller?

UALink Controller is a UALink IP core from Cadence Design Systems, Inc. listed on Semi IP Hub.

How should engineers evaluate this UALink?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this UALink IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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