MIPI SoundWire I3S Verification IP

SmartDV’s MIPI SoundWire I3S Verification IP is designed to verify the SoundWire I3S interface—an extension of the SoundWire standard for high-performance multichannel audio applications. Fully compliant with the MIPI SoundWire I3S specification, this VIP enables accurate and efficient verification of low-latency, synchronized audio transport between SoCs and external audio components.

The VIP supports major verification languages, including SystemVerilog and Verilog, and integrates seamlessly with methodologies such as UVM, OVM, and VMM. It is simulator-independent and compatible with all leading EDA vendors’ simulators, providing flexibility across simulation environments.

With configurable master and slave agents, support for frame-based transfers, synchronized channel handling, integrated protocol checkers, and detailed coverage metrics, SmartDV’s MIPI SoundWire I3S VIP empowers verification teams to validate high-bandwidth, multi-channel audio interfaces in mobile, automotive, and professional audio applications.

• Full MIPI SoundWire I3S Master, Slave and Monitor functionality
• Supports MIPI Soundwire-I3S Bus Draft Specification v0.4r06.
• Supports system with one master and one or more slaves (upto 8 slaves).
• Supports LVDS PHY for higher speed and a single-ended CMOS PHY for lower speed systems.
• Supports reset and link power management.
• Supports 8b/10b encoding and decoding.
• Supports the following transfer types,
  • Info transfer
  • Read transfer
  • Write transfer
  • Multicast write transfer
  • Multicast commit transfer
  • Multi Phase read transfer
• Supports all control data and command formats in master and slave.
• Supports Transport of payload data.
• Supports Timing information from the Master enabling the Slave both to send and receive data bits and to generate audio sampling events.
• Supports for multiple channels and both PDM and PCM data encodings.
• Supports Row based structure of the bitstream.
• Supports for low latency transmission.
• Supports In-band signaling of interrupt conditions.
• Supports In-band signaling of wake-up requests.
• Supports System-wide stream synchronization.
• Supports Embedded command channel for reading and writing control parameters and reporting status.
• Supports clock data recovery.
• Supports Jitter insertion.
• Supports below transport and protocol errors,
  • Bad symbol error
  • Bad token error
  • Bad HD10 token Error
  • CRC error
  • Unexpected token protocol error
  • Unexpected phase protocol error
• Status counters for various events in bus.
• Detects and notifies the test bench of all protocol and timing errors.
• Callbacks in master, slave and monitor for user processing of data.
• MIPI Soundwire – I3S Verification IP comes with complete test suite to test every feature of MIPI Soundwire – I3S specification.
• Functional coverage for complete MIPI Soundwire – I3S features.

• Faster testbench development and more complete verification of MIPI SoundWire I3S designs.
• Easy to use command interface simplifies testbench control and configuration of master and slave.
• Simplifies results analysis.
• Runs in every major simulation environment.

• Complete regression suite containing all the MIPI SoundWire I3S testcases.
• Examples showing how to connect various components, and usage of Master,Slaves and Monitor.
• Detailed documentation of all class, task and function's used in verification env.
• Documentation also contains User's Guide and Release notes.