Vendor: Cadence Design Systems, Inc. Category: Soundwire

Simulation VIP for MIPI SoundWire-I3S

Best-in-class MIPI® SoundWire-I3Ssm (SWI3S) Verification IP for your IP, SoC, and system-level design testing.The Cadence® Verifi…

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Overview

Best-in-class MIPI® SoundWire-I3Ssm (SWI3S) Verification IP for your IP, SoC, and system-level design testing.

The Cadence® Verification IP (VIP) for SoundWire-I3S (SWI3S) is designed for easy integration in test benches at the IP, system-on-chip (SoC), and system level. The VIP for SWI3S runs on all simulators and supports SystemVerilog along with the widely adopted Universal Verification Methodology (UVM). This enables verification teams to reduce the time spent on environment development and redirect it to cover a larger verification space, accelerate verification closure, and ensure end-product quality. It supports Manager, and a configurable number of peripherals (1-8).

Supported Specifications: MIPI SoundWire-I3S specification version 0.4r36, October 2022

Key features

  • PHYs
    • Supports LC PHY and DLV PHY
  • Interfaces
    • Supports serial interface
  • Resets
    • Ability to perform power on reset and bus reset
  • Peripheral Devices
    • Multiple peripherals supported (up to 8)
  • Command Transfer
    • Manager and peripheral devices can perform ping, write, read command transfer only
  • Clock and Data recovery
    • Peripheral can lock to row syncs to generate CDR clock
  • Strength Driving
    • Manager and peripheral supports driving and identifying different driving strengths modeled as Verilog net strengths
  • Glitch Filtering
    • Manager and peripheral can filter glitches during Link control and Reset
  • Phy Control Register
    • Register to control PHY behavior (DoBusReset, StopLink, and Peripheral WakeUp, etc.)
  • Error Injection
    • Manager and peripheral support 8B-10B encoding errors and inserting glitches during bus reset
  • Transport and Protocol errors
    • Manager and peripheral can detect transport and protocol errors
  • Codeword Endianness
    • Supports Little and Big endian modes
  • Link control sequences
    • Supports bus reset, coldstandby-wake, and sleep-wake sequences

Block Diagram

Simulation VIP for MIPI SoundWire-I3S block diagram

Files

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Specifications

Identity

Part Number
Simulation VIP for MIPI SoundWire-I3S
Vendor
Cadence Design Systems, Inc.

Provider

Cadence Design Systems, Inc.
HQ: USA
If you want to achieve silicon success, let Cadence help you choose the right IP solution and capture its full value in your SoC design. Cadence® IP solutions offer the combined advantages of a high-quality portfolio, an open platform, a modern IP factory approach to quality, and a strong ecosystem. Now you can tackle IP-to-SoC development in a system context, focus your internal effort on differentiation, and leverage multi-function cores to do more, faster. The Cadence IP Portfolio includes silicon-proven Tensilica® IP cores, analog PHY interfaces, standards-based IP cores, verification IP cores, and other solutions as well as customization services for current and emerging industry standards. The Cadence IP Factory provides you with an automated approach to the customization, delivery, and verification of SoC IP. As a result, you can spend more time on differentiation, with the assurance that you'll meet your performance, power, and area requirements. Choosing Cadence IP enables you to design with confidence because you have more freedom to innovate your SoCs with less risk and faster time to market.
Contact Cadence Design Systems, Inc.

Learn more about Soundwire IP core

How Arasan’s SoundWire PHY Can Elevate Your Next Audio SoC

In the race to build smaller, smarter, and more efficient devices, audio system-on-chips (SoCs) must meet increasingly demanding requirements: high fidelity, low latency, low power, and seamless integration. The SoundWire PHY from Arasan Chip Systems is engineered to meet these challenges and elevate your next audio SoC design from standard to standout.

Frequently asked questions about SoundWire IP cores

What is Simulation VIP for MIPI SoundWire-I3S?

Simulation VIP for MIPI SoundWire-I3S is a Soundwire IP core from Cadence Design Systems, Inc. listed on Semi IP Hub.

How should engineers evaluate this Soundwire?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Soundwire IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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