Vendor: Obsidian Technology Category: PLL

Low Power PLL for TSMC 40nm ULP

The OT3135 is a flexible low power clock multiplier PLL function with a wide range of input and output frequencies, and is design…

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TSMC 40nm ULP eFlash Silicon Proven View all specifications

Overview

The OT3135 is a flexible low power clock multiplier PLL function with a wide range of input and output frequencies, and is designed for TSMC 40nm, ULP CMOS processes.
 

Key features

  • Wide range M, P, and N integer dividers.
  • 40MHz – 600MHz output frequency range.
  • Input frequency range 1.4MHz – 32MHz.
  • 15pS RMS cycle to cycle jitter.
  • Lock-detect function.
  • Optional bypass function.
  • Level shifted IO.
  • Well-defined, fast startup behavior.
  • -40°C to 125°C temperature operation.
  • Small area: 0.03mm2 in 40nm CMOS.
  • 100µW typical power dissipation.
  • 0.82-1.1V digital and analog supplies.
  • Silicon proven.

Block Diagram

OT3135 block diagram

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Silicon Options

Foundry Node Process Maturity
TSMC 40nm ULP eFlash Silicon Proven

Specifications

Identity

Part Number
OT3135
Vendor
Obsidian Technology

Provider

Obsidian Technology
HQ: USA
About Obsidian Technology
  • Founded 1995
  • Privately owned consulting company
  • Diversified customer base
  • Self funded
About Obsidian IP
  • Early delivery of front-end models.
  • On-site support available, including transfer of source to your design environment.
  • Available on-site design review.
  • On-site training for source licensing.
  • Option to take ip though your own quality and review processes.
  • Characterization support.
  • Fast and flexible legal. We typically accept your standard bi-directional NDA.
  • Simple plain-language contracts.
Contact Obsidian Technology

Learn more about PLL IP core

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Specifying a PLL Part 3: Jitter Budgeting for Synthesis

This white paper is aimed at system architects and physical implementation leaders working on the design of SoCs. It can be confusing to understand the impact of different jitter sources and how to calculate a jitter budget when specifying a digital system. This white paper explains how jitter changes the period of a clock and how to ensure that jitter has correctly been accounted for in the calculations for timing closure.

Specifying a PLL Part 2: Jitter Basics

This article explains a some of the key terminology and parameters commonly used to describe jitter. It will also help clarify the most important parameters for a some PLL applications, allowing the designer to better understand what is required from a PLL.

Specifying a PLL Part 1: Calculating PLL Clock Spur Requirements from ADC or DAC SFDR

In high end RF systems, such as 5G radios, the requirements are so stringent that the source of this strongest unwanted tone can be the PLL. This article outlines how spurs in the input clock to the ADC or DAC may limit the SFDR. This in turn will set the requirements for the spurs for the input clock (from a PLL), in order to achieve a specific SFDR.

Achieving Groundbreaking Performance with a Digital PLL

This article compares analog, first-generation digital, and second-generation digital PLLs. It evaluates which type of PLL may be best in which situation. It further discloses a roadmap into other application areas, including general purpose / logic clocking, and regular low-jitter PLLs.

Frequently asked questions about PLL IP cores

What is Low Power PLL for TSMC 40nm ULP?

Low Power PLL for TSMC 40nm ULP is a PLL IP core from Obsidian Technology listed on Semi IP Hub. It is listed with support for tsmc Silicon Proven.

How should engineers evaluate this PLL?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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